ZPSD301 datasheet(26/85 Pages) STMICROELECTRONICS

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PSD3XX Family

12.0

Control Signals

(cont.)

12.5 A19/CSI

This pin is configured using PSDsoft to be either a chip select for the entire PSD device or

an additional PAD input. If your MCU can generate a chip-select signal, and you wish to

save power, use the PSD chip select feature. Otherwise, use this pin as an address or logic

input.

t When configured as CSI (active-low PSD chip select): a low on this pin keeps the PSD

in normal operation. However, when a high is detected on the pin, the PSD

enters Power-down Mode. See Tables 7A and 7B for information on signal states

during Power-down Mode. See section 16 for details about the reduction of power

consumption.

t When configured as A19, the pin can be used as an additional input to the PADs.

It can be used for address or logic. It can also be ALE/AS dependent or a transparent

input, which is determined by your PSDsoft design file. In A19 mode, the PSD is always

enabled.

Port

Configuration Mode(s)

State

AD0–A0/AD15/A15

All

Input (Hi-Z)

MCU I/O

Unchanged

Port Pins PA0–PA7

Tracking AD0/A0-AD7/A7

Input (Hi-Z)

Latched Address Out

Logic 1

MCU I/O

Unchanged

Port Pins PB0–PB7

Chip Select Outputs, CS0–CS7, CMOS

Logic 1

Chip Select Outputs, CS0–CS7, Open Drain

Hi-Z

Port Pins PC0–PC2

Address or Logic Inputs, A16-A18

Input (Hi-Z)

Chip Select Outputs, CS8–CS10, CMOS only

Logic 1

Table 7A. Signal States During Power-Down Mode

Internal Signal State

Component

Internal Signal

During Power-Down

PAD A and PAD B

CS0–CS10

Logic 1 (inactive)

CSADIN, CSADOUT1,

CSADOUT2, CSIOPORT,

Logic 0 (inactive)

ES0-ES7, RS0

All registers in CSIOPORT

N/A

address space, including:

Direction

Data

All unchanged

Page

PMR (turbo bit, ZPSD only)

Table 7B. Internal States During Power-down

NOTE: N/A = Not Applicable

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