ZPSD301 datasheet(20/85 Pages) STMICROELECTRONICS

20 / 85 page

NOTE: 1. The expression for CSADOUT2 must include the following write operation cycle signals:

For CRRWR = 0, CSADOUT2 must include WR = 0.

For CRRWR = 1, CSADOUT2 must include E = 1 and R/W = 0.

PSD3XX Family

INTERNAL

READ

CSADIN

INTERNAL

ALE

PA0 – PA7

A11– A15

A16 – A19

AD8– AD15

CSADOUT1

CSADOUT2

(1)

ALE or AS

AD0 –AD7

RD/E

WR or R / W

CONTROL

DECODER

LATCH

PAD

NOTE: 1. CMOS/OD determines whether the output is open drain or CMOS.

READ PIN

PORT A PIN

ENABLE

LATCHED

ADDR OUT

MCU

I/O

OUT

ADn/ Dn

READ DATA

WRITE DATA

ALE

READ DIR

WRITE DIR

RESET

CMOS / OD

(1)

DFF

LATCH

DIR

CONTROL

MUX

10.2.2 Port A (PA0-PA7) in Non-Multiplexed Address/Data Mode

In this mode, Port A becomes the low-order data bus byte of the chip. When reading an

internal location, data is presented on Port A pins to the MCU. When writing to an internal

location, data present on Port A pins from the MCU is written to the desired location.

10.0

I/O Port

Functions

(cont.)

Figure 5A. Port A Pin Structure

Figure 5B. Port A Track Mode

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