STW5095 datasheet(12/69 Pages) STMICROELECTRONICS

12 / 69 page

3 Functional Description

STw5095

12/69

3.3

Power up

STw5095 internal blocks can individually be switched on and off according to the user needs. A

general Power Up bit is present at bit 7 of CR0. See the following drawing to select the needed

block for the desired function. A fast-settling function is activated to quickly charge external

capacitors when the device is switched on (CAPLS, CAPLINEIN and CAPMIC).

3.4

Master clock

The master clock pin (AMCK) accepts any frequency from 4 MHz to 32 MHz. The 4-32 MHz

range is divided in sub-ranges that have to be programmed in bits CKRANGE in CR30. The

jitter and spectral properties of this clock have a direct impact on the DAC and ADC

performance because it is used to directly or by integer division drive the continuous-time to

sampled-time interfaces.

Note that AMCK clock des not need to have any relation to any other digital or analog input or

output.

Figure 2.

Power up block diagram

POWERUP

ENANA

STw5095

ENMIXL

ENHPVCM

ENHPL

ENLS

ENHPR

ENMICR

ENMICL

ENLINR

ENLINL

ENOSC

ENADCR

ENADCL

ENDACR

ENDACL

AUDIO I/F

ENLOL

ENLOR

ENHSD

ENPLL

DAMAST

ENDAOCK

ADMAST

ENADOCK

MBIAS

ENAMCK

ENDACKGEN

ENADCKGEN

ENOSC=1

ENOSC=0

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