STW5095 datasheet(13/69 Pages) STMICROELECTRONICS

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STw5095

3 Functional Description

13/69

AMCK can be either a squarewave or a sinewave, bit AMCKSIN in CR30 selects the proper

input mode. When a sinewave is used as input, AMCK pin must be decoupled with a capacitor.

Specification for sinusoidal input can be found in

Section 9.2: AMCK with sinusoidal input on

page 53.

The AMCK clock is not needed when only analog functions are used. For this purpose an

internal oscillator with no external components can be used to operate the device (see

Analog-only operation on page 17).

3.5

Data rates

STw5095 supports any data rate in 2 ranges: 8 kHz to 48 kHz and 88 kHz to 96 kHz. The range

is selected with bits DA96K and AD96K in CR29 for AD and DA paths respectively.

Note:

When AD96K=1 it is required to have DA96K=1.

The rates are fully independent in A/D and D/A paths. Moreover the rates do not have to be

specified to the device and they can change on the fly, within one range, while data is flowing.

The 2 audio data interfaces (for A/D and D/A) can independently operate in master or slave

mode.

3.6

Clock generators and master mode function

STw5095 provides 2 internal clock generators that can drive, if needed, the audio interfaces

(master mode), and/or two independent master clocks.

The AMCK clock input frequency is internally raised via a PLL to obtain a clock (MCK) in the

range 32 MHz to 48 MHz. The ratio MCK/AMCK is defined in CR30 (see MCKCOEFF in

Section 4.6 on page 32).

MCK is used to obtain, by fractional division, the oversampled clock (OCK), word clock (SYNC)

and bit clock (CK), that will therefore have edges aligned with MCK (the OCK period can have

jitter of 1 MCK period).

The frequency of OCK, SYNC and CK is set with DAOCKF in CR21/20 for DA interface, and

ADOCKF in CR24/23 for AD interface.

The ratio between OCK and SYNC clocks is selected with bit DAOCK512 in CR22 for DA

interface and bit ADOCK512 in CR25 for AD interface. The ratio between CK and SYNC clocks

depends on the selected interface format (see

Audio digital interfaces paragraph below). Note

that SPI format can only be slave.

The ADOCK and DAOCK output clocks are activated by bits ENADOCK and ENDAOCK

respectively, while master mode generation is activated with two bits: first ADMAST (DAMAST)

sets ADSYNC and ADCK (DASYNC and DACK) pins as outputs, then ADMASTGEN

(DAMASTGEN) generates the SYNC and CK clocks. The logical value at SYNC and CK pins

before data generation depends on the interface selected format.

See description of CR20 to CR25 for further details.

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