STW5095 datasheet(37/69 Pages) STMICROELECTRONICS

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STw5095

4 Control Registers

37/69

4.9

Interrupt control and control interface SPI out mode

Note:

Value at IRQ pin is:

CR#

(hex)

Description

D7D6D5D4

D2D1

Def.

CR31 (1Fh)

interrupt Mask

VLSHEN

PUSHBEN

HSDETEN

VLSHMSK

PUSHBMSK

HSDETMSK

OVFMSK

PORMSK

0000 0000

CR32 (20h)

Interrupt Status

VLSH

PUSHB

HSDET

VLSHEV

PUSHBEV

HSDETEV

OVFEV

POREV

0000 0000

CR33 (21h)

Misc. Control

SPIOHIZ

SPIOSEL(1:0)

IRQCMOS

OVFDA

OVFAD

0000 0000

Bits

Name

Value

CR31 Description

Def.

7VLSHEN

VLSH status can be seen at IRQ output

VLSH status is masked

PUSHBEN

PUSHB status can be seen at IRQ output

PUSHB status is masked

HSDETEN

HSDET status can be seen at IRQ output

HSDET status is masked

4VLSHMSK

VLSH event can be seen at IRQ output

VLSH event is masked

PUSHBMSK

PUSHB event can be seen at IRQ output

PUSHB event is masked

HSDETMSK

HSDET event can be seen at IRQ output

HSDET event is masked

1OVFMSK

OVF event can be seen at IRQ output

OVF event is masked

0PORMSK

POR event can be seen at IRQ output

POR event is masked

IRQ

(1 or Z) when (CR31 & CR32) = 00 hex

when (CR31 & CR32)

00 hex

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