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STW4810 数据表(PDF) 29 Page - STMicroelectronics

部件名 STW4810
功能描述  Power Management for Multimedia Processors
PDF  72 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STW4810 数据表(HTML) 29 Page - STMicroelectronics

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STw4810
4 Functional description
Rev3
29/72
4.2.6
IT generation
STw4810 has three interrupt balls:
IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is plugged
this interrupt is activated to wake up the host or the modem, depends of application (active low).
USBINTn: This interrupt ball is dedicated to USB protocol and sent to multimedia processor
VDDOK: This ball has two functions:
- When high, it indicates that VIO_VMEM and VCORE output voltages are within the right
range and that the device internal temperature is below the maximum allowed temperature.
- When low, it indicates that output regulators (VCORE or VIO_VMEM) are not regulated
properly or PWREN = “0”, or that the temperature is above the allowed threshold (see
Thermal
shut-down section). The interruption source in the application register (address 11h) needs to
be checked.
4.2.7
Clock switching and control
This block generates the clock used by the DC/DC converter (USB charge pump, step-down
VIO_VMEM and step-down VCORE). STw4810 is able to sustain the master clock frequencies
of 26 MHz, 19.2MHz and 13 MHz. It can also sustain dedicated MASTER_CLK signal in the
frequency range of 750KHz to 1MHz. If the clock is not detected the internal oscillator is
automatically selected.
Note:
When present the Master clock should remain connected up to Sleep mode.
Figure 9.
Clock switching between master and internal clock (1)
INT_OSC
PON
INT_OSC_OK
MASTER_CLK_OK
PDN_INT_OSC
CONTROL_SWITCH
STEP_DOWN_CLK
Third rising edge after switching
internal clock
external clock
transition
* Phase delay is less than 90 between int and ext clock
MASTER_DIV_CLK



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