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数据搜索系统，热门电子元器件搜索 |
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STW4810 数据表(PDF) 49 Page - STMicroelectronics |
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STW4810 数据表(HTML) 49 Page - STMicroelectronics |
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49 / 72 page  STw4810 5 Electrical and timing characteristics Rev3 49/72 5.3.5 LDO regulators VPLL Table 39. LDO regulators - VPLL Symbol Description Test conditions Min. Typ. Max. Units VPLL Regulator in Normal Mode / Otherwise specified, VPLL = 1.8 V VBAT Input power supply Battery voltage 2.7 3.6 4.8 V VOUT Output voltage VPLL_SEL[1:0] 11 (default) 10 01 00 -3% 1.8 1.3 1.2 1.05 +3% V IOUT Output current 3.5 10 mA ISHORT Short-circuit limitation 95 130 165 mA IQ Quiescent current IOUT = 0 mA 30 40 µA ILKG Power-down current EN_VPLL = 0 1 µA PSRR(1) 1. Guaranteed by design Power supply rejection Vpp = 0.3 V f < 10 kHz 10 kHz < f <100 kHz 55 45 dB dB LIR Line regulation VBAT: [2.7; 4.8]V 5 mV LDR Load regulation IOUT: [0.1; 10] mA 10 mV LIRT Transient line regulation ∆VBAT = 300 mV tR = tF = 10 µs 1 mV LDRT Transient load regulation IOUT = [0.1; 10] mA tR = tF = 1 µs 1 mV En(1) Noise density at 1 KHz BW = 100 Hz 250 nV rms Hz ------------- |
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