STW4810 datasheet(30/72 Pages) STMICROELECTRONICS

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4 Functional description

STw4810

30/72

Rev3

4.3

Power management module

STw4810 includes several regulators that supply the multimedia processor and its peripherals.

All regulators can work in different modes depending on the processor needs.

When the STw4810 is in ‘Low Current Mode’”, the output current is reduced to save energy via

the lower quiescent current. The nominal mode is called high power mode (HPM). The mode is

selected by PWREN signal according to both multimedia processor and STw4810 state.

When PWREN = “0”, sleep mode is selected. HPM is selected as default when PWREN = “1”.

Each regulator has a dedicated battery power supply. It can be powered down by a signal

called PDN_regulator_name as shown in the

Figure 2: STw4810 block diagram. In this mode,

the regulator is switched off and only a leakage current is present (max. 1µA). VCORE, VAUX

and VPLL output voltages are programmable, through main I2C interface, using the

“Regulator”_SEL[x:0] bits of the POWER CONTROL registers (

Table 21 to Table 26).

In addition, an output current limitation prevents high current delivery in case of output short

circuit.

All multimedia processor power supplies have the same soft start to prevent leakage in the

multimedia processor device during the start-up phase. There is an exception with VAUX which

can be started independently.

4.3.1

Bandgap, biasing and references

Figure 10. Block diagram of biasing and references of the device

4.3.2

VCORE regulator: DC/DC STEP- DOWN regulator

This regulator drives the core of the multimedia processor. VCORE is a DC/DC step-down

regulator that generates the regulated power supply with very high efficiency. The 15 voltage

levels enable dynamic voltage and frequency scaling suitable for any supply voltage of CMOS

process, they also follow the processor process roadmap. The regulated output voltage levels

are adjustable by the power control registers (

Table 21), via the main I2C interface (SDA, SCL).

The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to

generate the switching clock of the SMPS. When this clock is not available, regulators run the

internal RC oscillator.

All internal

references

VREF_18

All internal

biasing

BIAS GENERATOR

VOLTAGE REFERENCE

CONTROL

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