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M69KB096AB 数据表(PDF) 52 Page - STMicroelectronics |
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M69KB096AB 数据表(HTML) 52 Page - STMicroelectronics |
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52 / 73 page  9 DC and AC parameters M69KB096AB 52/73 Table 20. Clock Related AC Timings Table 21. Synchronous Burst Read AC Characteristics Symbol Alt. Parameter 104MHz 80MHz Unit Min Max Min Max fCLk fCLk Clock frequency 104 80 MHz tKHKH tCLK Clock Period 9.62 12.5 ns tR tF tKHKL Clock Rise Time Clock Fall Time 1.6 1.8 ns tKHKL tKLKH tKP Clock High to Clock Low Clock Low to Clock High 34 ns Symbol Alt. Parameter(1) 104MHz 80MHz Unit Min Max Min Max tAVQV tAA Address Valid to Output Valid (Fixed Latency) 70 70 ns tLLQV tAADV Latch Enable Low to Output Valid (Fixed Latency) 70 70 ns tKHQV1 tABA Burst to Read Access Time (Variable Latency) 35 46 ns tKHQV2 tACLK Clock High to Output Delay 7 9 ns tGLQV tBOE Delay From Output Enable Low to Output Valid in Burst mode 20 20 ns tEHEL (2) tCBPH Chip Enable High between Subsequent Operations in Full-Synchronous or NOR-Flash mode. 56 ns tELEH (2) tCEM Chip Enable Pulse Width 4 4 µs tELTV tLLTV tCEW Chip Enable Low to WAIT Valid Latch Enable Low to WAIT Valid 1 7.5 1 7.5 ns tELQV tCO Chip Enable Low to Output Valid 70 70 ns tELKH tCSP Chip Enable Low to Clock High 3 4 ns tKHAX tKHBH tKHWL tKHEH tKHLH tKHQX tHD Hold Time From Active Clock Edge 2 2 ns tEHQZ tEHTZ (3) tHZ Chip Enable High to Output Hi-Z or WAIT Hi-Z 8 8 ns tKHTX tKHTV tKHTL Clock High to WAIT Valid 7 9 ns tGHQZ (3) tOHZ Output Enable High to Output Hi-Z 8 8 ns |
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