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M69KB096AB 数据表(PDF) 63 Page - STMicroelectronics |
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M69KB096AB 数据表(HTML) 63 Page - STMicroelectronics |
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63 / 73 page  M69KB096AB 9 DC and AC parameters 63/73 Figure 32. Burst Write Interrupted by Burst Write or Read AC Waveforms 1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). All Burst operations are given for variable latency and no refresh collision. 2. The Burst Write is interrupted during the first allowable clock cycle, i.e. after the first Word written to the memory. 3. The Chip Enable signal, E, can remain Low, VIL, between burst operations, but it must not remain Low for longer than tELEH. |
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