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M69KB096AB 数据表(PDF) 17 Page - STMicroelectronics

部件名 M69KB096AB
功能描述  64 Mbit (4Mb x 16), 104MHz Clock Rate, 1.8V Supply, Bare Die, Burst PSRAM
PDF  73 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M69KB096AB 数据表(HTML) 17 Page - STMicroelectronics

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M69KB096AB
5 Standard Asynchronous operating modes
17/73
Table 3.
Standard Asynchronous Operating Modes
Asynchronous
Modes(1)(2)
1.
The Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in Standby and
Deep Power-Down modes.
2.
The device must have been configured to operate in asynchronous mode by setting BCR15 to ‘1’ (default value).
Power
E
W
G
UB
LB
CR
A19 A18
A0-A17
A20-A21
DQ0-DQ7
DQ8-DQ15
Word Read
Active
(ICC)
VIL
VIH
VIL
VIL
VIL
VIL
Valid
Output
Valid
Output
Valid
Lower Byte
Read
VIL
VIH
VIL
VIL
Valid
Output
Valid
High-Z
Upper Byte
Read
VIL
VIL
VIH
VIL
Valid
High-Z
Output
Valid
Word Write
VIL
X
VIL
VIL
VIL
Valid
Input Valid
Input Valid
Lower Byte
Write
X
VIH
VIL
VIL
Valid
Input Valid
Invalid
Upper Byte
Write
X
VIL
VIH
VIL
Valid
Invalid
Input Valid
Read
Configuration
Register
(CR Controlled
Method)
VIH VIL
XX
VIH
00(RCR)
10(BCR)
X1(DIDR)
X
BCR/
RCR/DIDR
Content
Program
Configuration
Register (CR
Controlled)(3)
3.
BCR and RCR only.
VIL
XX
X
00(RCR)
10(BCR)
(4)
4.
A18 and A19 are used to select the BCR, RCR or DIDR registers.
BCR/
RCR Data
X
Output Disable/
No Operation
Active
(ICC)
VIH VIH
XX
VIL
XX
X
High-Z
Deep
Power-Down(5)
5.
Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E must be maintained High, VIH, during Deep Power-
Down mode.
Deep
Power-
Down
(ICCPD)
VIH
XX
X
X
X
X
X
X
High-Z
Standby
Standby
(IPASR)
VIH
XX
X
X
X
X
X
X
High-Z



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