M69KB096AB datasheet(29/73 Pages) STMICROELECTRONICS

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M69KB096AB

7 Configuration Registers

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7.3

Bus Configuration Register

The Bus Configuration Register (BCR) defines how the PSRAM interacts with the system

memory bus. All the device operating modes are configured through the BCR, except the Page

mode which is configured through the RCR.

Refer to Table 9 for the description of the Bus Configuration Register Bits.

7.3.1

Operating Mode Bit (BCR15)

The Operating Mode bit allows the Synchronous mode or the Asynchronous mode (default

setting) to be selected. Selecting the Synchronous mode will allow the device to operate either

in NOR Flash mode or in full Synchronous Burst mode.

The device will automatically detect that the NOR Flash mode is being used by monitoring a

rising edge of the Clock signal, K, when L is Low. If this should not be the case, the device

operates in full Synchronous mode.

7.3.2

Latency Type (BCR14)

The Latency Type bit is used to configure the latency type. When the Latency Type bit is set to

‘0’, the device operates in variable latency mode (only available for Synchronous Read mode).

When it is ‘1’, the fixed latency mode is selected and the latency is defined by the values of bits

BCR13 to BCR11.

Refer to Figures 3 and 4 for examples of fixed and variable latency configuration.

7.3.3

Latency Counter Bits (BCR13-BCR11)

The Latency Counter bits are used to set the number of clock cycles between the beginning of

a read or write operation and the first data output or input.

The Latency Counter bits can only assume the values shown in Table 9: Bus Configuration

7.3.4

WAIT Polarity Bit (BCR10)

The WAIT Polarity bit indicates whether the WAIT output signal is active High or Low. As a

consequence, it also determines whether the WAIT signal requires a pull-up or pull-down

resistor to maintain the de-asserted state (see Figure 10: WAIT Polarity).

By default, the WAIT output signal is active High.

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