M69KB096AB datasheet(19/73 Pages) STMICROELECTRONICS

19 / 73 page

M69KB096AB

6 Synchronous Operating modes

19/73

6.2

Full Synchronous mode

In Full Synchronous mode, the device performs read and write operations synchronously.

Synchronous Read and Write operations are performed at Word level. The initial Burst Read

and Write access latches the Burst start address. The number of Words to be output or input

during Synchronous Read and Write operations is controlled by bits 0 to 2 of the BCR.

During Burst Read and Write operations, the first data will be output after a number of clock

cycles defined by the Latency value.

Programming the registers (BCR and RCR) and reading the registers (BCR, RCR and DIDR)

can be performed using the CR controlled method in Full Synchronous mode.

Full Synchronous operations are described in Table 7: Full Synchronous Mode.

6.3

Synchronous Burst Read and Write

During Synchronous Burst Read or Write operations, addresses are latched on the rising edge

of the Clock K when L is Low and data are latched on the rising edge of K. The Write Enable,

W, signal indicates whether the operation is going to be a read (W=VIH) or a write (W=VIL).

The WAIT output will be asserted as soon as a Synchronous Burst operation is initiated and will

be de-asserted to indicate when data are to be transferred to (or from) the memory array.

The Burst Length is the number of Words to be output or input during a Synchronous Burst

Read or Write operation. It can be configured as 4, 8, 16 or 32 Words or continuous through bit

BCR0 to BCR2 or the Burst Configuration Register.

The Latency defines the number of clock cycles between the beginning of a Burst Read

operation and the first data output (counting from the first Clock edge where L was detected

Low) or between the beginning of a Burst Write operation and the first data input. The Latency

can be set through bits BCR13 to BCR11 of the Bus Configuration Register (see Table 4:

Operating Frequency versus Latency).

The latency can also be configured to fixed or variable by programming bit BCR14. By default,

the Latency Type is set to variable. Synchronous Read operations are performed in both fixed

and variable latency mode while Synchronous Write operations are only performed with fixed

latency.

See Figures 24, 26, and Figures 30, 31, for details on Synchronous Read and Write AC

waveforms, respectively.

6.3.1

Variable Latency

In Variable Latency mode, the latency programmed in the BCR is not guaranteed and is

maintained only if there is no conflict with a refresh operation. The Latency set in the BCR is

applicable only for an initial burst read access, when no refresh request is pending. For a given

latency value, the Variable Latency mode allows higher operating frequencies than the Fixed

Latency mode (see Table 4: Operating Frequency versus Latency and Figure 3: Latency

Configuration (Variable Latency Mode, No Refresh Collision)).

Burst Write operations are always performed at fixed latency, even if BCR14 is configured to

Variable Latency (see Section 6.3.2: Fixed Latency).

Monitoring of the WAIT signal is recommended for reliable operation in this mode. See Figure

24. and 31 for details on Synchronous Burst Read and Write AC waveforms in Variable Latency

mode.

M69KB096AB 数据表(PDF) 19 Page - STMicroelectronics

M69KB096AB 数据表(HTML) 19 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表下载