AT25QL641 datasheet(52/77 Pages) DIALOG

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AT25QL641

DS-25QL641–130E–10/2018

Figure 7-55. Set Read Parameters Instruction (QPI Mode)

7.35

Enable Reset (66h) and Reset (99h)

For eight-pin packages, the AT25QL641 provide a software Reset instruction instead of a dedicated RESET pin.

Once the Reset instruction is accepted, any ongoing internal operations are terminated and the device returns to its

default power-on state and loses all the current volatile settings, such as Volatile Status Register bits, Write Enable

Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit setting, Read parameter setting and

Wrap bit setting.

The ‘Enable Reset’ (66h) and ‘Reset’ (99h) instructions can be issued in either SPI mode or QPI mode. To avoid

accidental reset, both instructions must be issued in sequence. Any other instructions other than ‘Reset’ (99h) that

occur after the ‘Enable’ (66h) instruction disables the reset enable state. As such, a new sequence of ‘Enable Reset’

(66h) and ‘Reset’ (99h) is needed to reset the device. Once the Reset instruction is accepted by the device takes

approximately t

RST = 30 µs to reset. During this period, no instructions are accepted.

Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset

instruction sequence is accepted by device. It is recommended to check the BUSY bit and the SUS bit in Status Register

before issuing the Reset instruction sequence.

Figure 7-56. Enable Reset and Reset Instruction (SPI Mode)

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