AT25QL641 datasheet(12/77 Pages) DIALOG

12 / 77 page

AT25QL641

DS-25QL641–130E–10/2018

6.5

Sector/Block Protect (SEC)

The Sector protect bit (SEC) is a non-volatile bit (S6) that controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB Sectors

(SEC = 1) or 64 KB blocks (SEC = 0) in the Top (TB = 0) or the Bottom (TB = 1) of the array as shown in the Status Register

Memory protection table. The default setting is SEC = 0.

6.6

Status Register Protect (SRP1, SRP0)

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The

SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time

programmable (OTP) protection.

Note: 1. When SRP1, SRP0=(1,0), a power down, power-up cycle will change SRP1, SRP0 to(0,0) state.

6.7

Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read/write bit (S9) that allows Quad operation. When the QE bit is set to

a 0 state (factory default) the WP pin and HOLD are enabled. When the QE pin is set to a 1 the Quad I/O

2 and I/O3 pins

are enabled.

WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the WP or HOLD

pins are tied directly to the power supply or ground.

6.8

Complement Protect (CMP)

The Complement Protect bit (CMP) is a non-volatile read/write bit (S14). It is used in conjunction with SEC, TB, BP2,

BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set

by SEC, TB, BP2, BP1 and BP0 is reversed. For instance, when CMP = 0, a top 4KB sector can be protected while the

rest of the array is not; when CMP = 1, the top 4KB sector becomes unprotected while the rest of the array becomes

read-only. For more information, refer to Table and Table 6-5 below. The default setting is CMP = 0.

6.9

Erase/Program Suspend Status (SUS)

The Suspend Status bit (SUS) is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program

Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power

down, power-up cycle.

Table 6-3.

Protection Types

SRP1

SRP0

Type of Protection

Description

Software Protection

WP pin no control. The register can be written to after a Write Enable

command, WEL = 1 (factory default)

Hardware Protected

When WP pin is low the Status Register locked and can not be written

to.

Hardware

Unprotected

When WP pin is high the Status register is unlocked and can be

written to after a Write Enable command, WEL = 1.

Power Supply

Lock-Down

Status Register is protected and cannot be written to again until the

next power down, power-up cycle(1)

One Time Program Status Register is permanently protected and cannot be written to.

AT25QL641 数据表(PDF) 12 Page - Dialog Semiconductor

AT25QL641 数据表(HTML) 12 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

数据表下载