AT25QL641 datasheet(2/77 Pages) DIALOG

2 / 77 page

DS-25QL641–130E–10/2018

Features

Single 1.7V - 2.0V Supply

Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI) compatible

Supports SPI Modes 0 and 3

Supports Dual Output Read and Quad I/O program and read

Supports QPI program and read

133 MHz maximum operating frequency

Clock-to-Output (t

V1) of 6 ns

Up tp 66 MB/s continuous data transfer rate

Quad enabled (factory default setting: see Section 6.7)

Full chip erase

Flexible, optimized erase architecture for code and data storage applications

0.6 ms typical Page Program (256 Bytes) time

60 ms typical 4 Kbyte Block Erase time

200 ms typical 32 Kbyte Block Erase time

350 ms typical 64 Kbyte Block Erase time

Hardware controlled locking of Status registers via WP pin

4 Kbit secured One-Time Programmable (OTP) security register

Hardware write protection

Serial Flash Discoverable Parameters (SFDP) register

Flexible programming

Byte/page program (1 to 256 Bytes)

Dual or quad input byte/page program (1 to 256 Bytes)

Erase/program suspend and resume

JEDEC standard manufacturer and device ID read methodology

Low power dissipation

2 µA Deep Power-Down (DPD) current (typical)

10 µA Standby current (typical)

5 mA Active read current (typical)

Endurance: 100,000 program/erase cycles (4KB, 32KB or 64KB blocks)

Data Retention: 20 years

Industrial temperature range: -40 °C to +85 °C

Industry standard green (Pb/Halide-free/RoHS compliant) package options

8-lead SOIC (0.208” Wide EIAJ)

8-pad DFN (6 x 5 x 0.6 mm)

8-ball WLCSP (dBGA)

AT25QL641

64-Mbit, 1.7V Minimum

SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

AT25QL641 数据表(PDF) 2 Page - Dialog Semiconductor

AT25QL641 数据表(HTML) 2 Page - Dialog Semiconductor

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