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AT25QL641

DS-25QL641–130E–10/2018

Device Operation

4.1

Standard SPI Operation

The AT25QL641 features a serial peripheral interface on four signals: Serial Clock (SCK). Chip Select (CS), Serial

Data Input (SI) and Serial Data Output (SO). Standard SPI instructions use the SI input pin to serially write instructions,

addresses or data to the device on the rising edge of SCK. The SO output pin is used to read data or status from the

device on the falling edge of SCK.

SPI bus operation Modes 0 (0, 0) and 3 (1, 1) are supported. The primary difference between Mode 0 and Mode 3

concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not being transferred

to the Serial Flash. For Mode 0 the SCK signal is normally low on the falling and rising edges of CS. For Mode 3 the

SCK signal is normally high on the falling and rising edges of CS.

4.2

Dual SPI Operation

The AT25QL641 supports Dual SPI operation. This instruction allows data to be transferred to or from the device at two

times the rate of the standard SPI. The Dual Read instruction is ideal for quickly downloading code to RAM upon power-

up (code-shadowing) or for execute-in-place (XiP) non-speed-critical code directly from the SPI bus. When using Dual

SPI instructions the SI and SO pins become bidirectional I/0 pins; I/O

0 and I/O1.

4.3

Quad SPI Operation

The AT25QL641 supports Quad SPI operation. This instruction allows data to be transferred to or from the device at

four times the rate of the standard SPI. The Quad Read instruction offers a significant improvement in continuous

and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus. When

using Quad SPI instruction the SI and SO pins become bidirectional I/O

0 and I/O1, and the WP and HOLD pins become

I/O

2 and I/O3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be

set.

4.4

QPI Operation

The AT25QL641 is shipped with the Quad Enable bit set and the device powers up in QPI mode. When using QPI

instructions, the SI and SO pins become bidirectional I/O0 and I/O1, and the WP and HOLD pins become I/O2 and I/O3

respectively.

The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via SI pin in eight

serial clocks. The QPI mode utilizes all four I/O pins to input the instruction code, thus only two serial clocks are required.

This can significantly reduce the SPI instruction overhead and improve system performance in an XiP environment.

Standard/ Dual/ Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given time, Enable

QPI (38h) and Disable QPI (FFh) instructions are used to switch between these two modes. Upon power-up or after

software reset using Reset (99h) instruction, the default state of the device is Standard/Dual/Quad SPI mode.

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