AT25QL641 datasheet(10/77 Pages) DIALOG

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AT25QL641

DS-25QL641–130E–10/2018

Write Protection

To protect inadvertent writes by the possible noise, several means of protection are applied to the Flash memory.

5.1

Write Protect Features

The write protect features are listed below.

While Power-on reset, all operations are disabled and no instruction is recognized.

An internal time delay of t

PUW can protect the data against inadvertent changes while the power supply is outside

the operating specification. This includes the Write Enable, Page Program, Block Erase, Chip Erase, Write Security

For data changes, Write Enable instruction must be issued to set the Write Enable Latch (WEL) bit to “0”. Power-

up, Completion of Write Disable, Write Status Register, Page Program, Block Erase and Chip Erase are subjected to

this condition.

Status Register protect (SRP) and Block protect (SEC, TB, BP2, BP1, and BP0) bits may be used to configure a

portion of the memory as read-only (software protection).

The Write Protect (WP) pin can be used to change the Status register (hardware control).

The Deep Power Down (DPD) mode provides extra protection from unexpected data changes as all instructions are

ignored under this status except for the ‘Release from Deep Power Down’ instruction.

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