USB82642 datasheet(41/64 Pages) MICROCHIP

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DS60001253F-page 41

USB82642

7.5.5

I2C EEPROM

The I2C EEPROM interface implements a subset of the I2C Master Specification (refer to the Philips Semiconductor

Standard I2C-Bus Specification [10] for details on I2C bus protocols). The device’s I2C EEPROM interface is designed

to attach to a single dedicated I2C EEPROM, and it conforms to the Standard-mode I2C Specification (100 kbit/s transfer

rate and 7-bit addressing) for protocol and electrical compatibility.

7.5.5.1

Implementation Characteristics

The device will only access an EEPROM using the sequential read protocol.

7.5.5.2

Pull-Up Resistor

The circuit board designer is required to place external pull-up resistors (10 kΩ recommended) on the SPI_DO/SDA_EP/

SPI_SPD_SEL and SPI_CLK/SCL_EP lines (per SMBus 1.0 Specification [11] and EEPROM manufacturer guidelines)

to VDD33 in order to assure proper operation.

7.5.5.3

I2C EEPROM Slave Address

Slave address is 1010000b. 10-bit addressing is NOT supported.

7.6

Default Configuration Option

The Microchip device can be configured via its internal default configuration. Please see Section 7.5.2, "EEPROM Data

Descriptor" for specific details on how to enable default configuration. Please refer to Table 7-1 for the internal default

values that are loaded when this option is selected.

7.7

Reset

There are two different resets that the device experiences. One is a hardware reset (either from the internal POR

(power-on reset) circuit or via the RESET_N pin) and the second is a USB bus reset.

7.7.1

EXTERNAL HARDWARE RESET_N

A valid hardware reset is defined as assertion of RESET_N for a minimum of 1 µs after all power supplies are within

operating range. While reset is asserted, the device (and its associated external circuitry) consumes less than IRST µA

of current from the upstream USB power source.

Assertion of RESET_N (external pin) causes the following:

All downstream ports are disabled, and PRTCTL power to downstream devices is removed.

The PHYs are disabled, and the differential pairs will be in a high-impedance state.

All transactions immediately terminate; no states are saved.

All internal registers return to the default state (in most cases, 00h).

The external crystal oscillator is halted.

The PLL is halted.

Note:

Extensions to the I2C Specification are not supported. The device acts as the master and generates the

serial clock SCL, controls the bus access (determines which device acts as the transmitter and which

device acts as the receiver), and generates the START and STOP conditions.

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