USB82642 datasheet(11/64 Pages) MICROCHIP

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DS60001253F-page 11

USB82642

VDD18PLL

1.8 V PLL Power Bypass

This pin is the 1.8 V power bypass for the PLL.

This pin requires an external bypass capacitor

of 1.0 µF.

If REG_EN is low, this pin serves as a power

supply (1.8 V) for the device.

VDDA33

3.3 V Analog Power

• 48VQFN - Pin 48 requires an external

bypass capacitor of 4.7 µF.

SPI Interface

SPI_CE_N

O12

SPI Chip Enable

This is the active low chip enable output. If the

SPI interface is enabled, drive this pin high in

power down states.

Leave open

SPI_CLK/

I/O12

SPI Clock

This is the SPI clock out to the serial ROM. See

Section 5.4, "ROM BOOT Sequence" for dia-

gram and usage instructions.

During reset, this pin is driven low.

Leave open

SCL_EP

When configured, this is the I²C EEPROM clock

pin.

Leave open

SPI_DO/

I/O12

SPI Data Out

This is the data out for the SPI port. See Section

5.4, "ROM BOOT Sequence" for diagram and

usage instructions.

Leave open

SDA_EP

This pin is the data pin when the device is con-

nected to the optional I²C EEPROM.

Leave open

SPI_SPD_SEL

This pin is used to pick the speed of the SPI

interface. During RESET_N assertion, this pin

will be tri-stated with the weak pull-down resistor

enabled. When RESET_N is negated, the value

on the pin will be internally latched, and the pin

will revert to SPI_DO functionality. Additionally,

the internal pull-down will be disabled.

: 30 MHz (deprecated and might be removed

in future versions)

: 60 MHz

If the latched value is 1, then the pin is tri-stated

when the chip is in the suspend state.

If the latched value is 0, then the pin is driven

low during a suspend state.

Leave open

SPI_DI

I/O12PD

SPI Data In

This is the data in to the controller from the SPI

ROM.

Leave open

TABLE 5-1:

USB82642 PIN DESCRIPTIONS (CONTINUED)

Symbol

48-Pin

VQFN

Buffer

Type

Description

If Pins not Used

Connection

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