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56F8335 数据表(PDF) 101 Page - Freescale Semiconductor, Inc

部件名 56F8335
功能描述  16-bit Digital Signal Controller
PDF  160 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

56F8335 数据表(HTML) 101 Page - Freescale Semiconductor, Inc

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Register Descriptions
56F8335 Technical Data, Rev. 1
Freescale Semiconductor
101
Preliminary
Figure 6-2 SIM Register Map Summary
6.5.1
SIM Control Register (SIM_CONTROL)
Figure 6-3 SIM Control Register (SIM_CONTROL)
6.5.1.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.1.2
OnCE Enable (OnCE EBL)—Bit 5
•
0 = OnCE clock to 56800E core enabled when core TAP is enabled
•
1 = OnCE clock to 56800E core is always enabled
Add.
Offset
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
$0
SIM_
CONTROL
R
0
0
0
0
0
0
0
0
0
0
ONCE
EBL0
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
W
$1
SIM_
RSTSTS
R
0
0
0
0
0
0
0
0
0
0
SWR
COPR
EXTR
POR
0
0
W
$2
SIM_SCR0
R
FIELD
W
$3
SIM_SCR1
R
FIELD
W
$4
SIM_SCR2
R
FIELD
W
$5
SIM_SCR3
R
FIELD
W
$6
SIM_MSH_
ID
R
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
W
$7
SIM_LSH_ID
R
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
W
$8
SIM_PUDR
R
0
PWMA1
CAN
EMI_
MODE
RESET
IRQ
XBOOT PWMB PWMA0
0
CTRL
0
JTAG
0
0
0
W
Reserved
$A
SIM_
CLKOSR
R
0
0
0
0
0
0
A23
A22
A21
A20
CLKDIS
CLKOSEL
W
$B
SIM_GPS
R
0
0
0
0
0
0
0
0
0
0
0
0
C3
C2
C1
C0
W
$C
SIM_PCE
R
EMI
ADCB
ADCA
CAN
DEC1
DEC 0
TMRD
TMRC
TMRB
TMRA
SCI1
SCI0
SPI1
SPI0
PWMB PWMA
W
$D
SIM_ISALH
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ISAL[23:22]
W
$E
SIM_ISALL
R
ISAL[21:6]
W
= Reserved
Base + $0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
0
0
0
ONCE
EBL
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
Write
RESET
0
0
00
00
0
0
0
0
0
0
0
0
0
0



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