56F8335 datasheet(104/160 Pages) FREESCALE

104 / 160 page

56F8335 Technical Data, Rev. 1

104

Freescale Semiconductor

Preliminary

6.5.5

Least Significant Half of JTAG ID (SIM_LSH_ID)

This read-only register displays the least significant half of the JTAG ID for the chip. This register reads

$401D.

Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)

6.5.6

SIM Pull-up Disable Register (SIM_PUDR)

Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these

resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the

appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not

muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See

Table 2-2 to identify which pins can deactivate the internal pull-up resistor.

Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)

6.5.6.1

Reserved—Bit 15

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.6.2

PWMA1—Bit 14

This bit controls the pull-up resistors on the FAULTA3 pin.

6.5.6.3

CAN—Bit 13

This bit controls the pull-up resistors on the CAN_RX pin.

6.5.6.4

EMI_MODE—Bit 12

This bit controls the pull-up resistors on the EMI_MODE pin.

Note:

In this package, this input pin is double-bonded with the adjacent VSS pin and this bit should be

changed to a 1 in order to reduce power consumption.

6.5.6.5

RESET—Bit 11

This bit controls the pull-up resistors on the RESET pin.

Base + $7

Read

Write

RESET

000

110

Base + $8

Read

PWMA1

CAN

EMI_

MODE

RESET

IRQ

XBOOT

PWMB

PWMA0

CTRL

JTAG

Write

RESET

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