MPC8544EBVTARGA datasheet(18/117 Pages) NXP

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 13 provides the DDR I/O capacitance when GVDD(typ) = 2.5 V.

Table 14 provides the current draw characteristics for MVREF.

6.2

DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1

DDR SDRAM Input AC Timing Specifications

Table 15 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 1.8 V.

Output low current (VOUT = 0.42 V)

IOL

16.2

—

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

Table 13. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS

CIO

Delta input/output capacitance: DQ, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

Table 14. Current Draw Characteristics for MVREF

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Current draw for MVREF

IMVREF

—500

μA1

Note:

1. The voltage regulator for MVREF must be able to supply up to 500 μA current.

Table 15. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—MVREF – 0.25

—

AC input high voltage

VIH

MVREF + 0.25

—

Table 12. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V (continued)

Parameter/Condition

Symbol

Min

Max

Unit

Notes

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