MPC8544EBVTARGA datasheet(68/117 Pages) NXP

68 / 117 page

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 48. Single-Ended Reference Clock Input DC Requirements

16.2.3

Interfacing With Other Differential Signaling Levels

With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are HCSL

(high-speed current steering logic) compatible DC-coupled.

Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be

used but may need to be AC-coupled due to the limited common mode input range allowed (100 to

400 mV) for DC-coupled connection.

LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock

driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to

AC-coupling.

NOTE

Figure 49 through Figure 52 are for conceptual reference only. Due to the

fact that clock driver chip's internal structure, output impedance and

termination requirements are different between various clock driver chip

manufacturers, it is very possible that the clock circuit reference designs

provided by clock driver chip vendor are different from what is shown

below. They might also vary from one vendor to the other. Therefore,

Freescale Semiconductor can neither provide the optimal clock driver

reference circuits, nor guarantee the correctness of the following clock

driver connection reference circuits. The system designer is recommended

to contact the selected clock driver chip vendor for the optimal reference

circuits with the MPC8544E SerDes reference clock receiver requirement

provided in this document.

SDn_REF_CLK

400 mV < SDn_REF_CLK Input Amplitude < 800 mV

MPC8544EBVTARGA 数据表(PDF) 68 Page - NXP Semiconductors