MPC8544EBVTARGA datasheet(80/117 Pages) NXP

80 / 117 page

MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

PCI Express

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the

TX UI.

NOTE

The reference impedance for return loss measurements is 50

Ω to ground for

both the D+ and D– line (that is, as measured by a vector network analyzer

with 50-

Ω probes, see Figure 57). Note that the series capacitors, CTX, are

optional for the return loss measurement.

Figure 57. Minimum Receiver Eye Timing and Voltage Compliance Specification

17.5.1

Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified within

0.2 inches of the package pins, into a test/measurement load shown in Figure 58.

NOTE

The allowance of the measurement point to be within 0.2 inches of the

package pins is meant to acknowledge that package/board routing may

benefit from D+ and D– not being exactly matched in length at the package

pin boundary.

Figure 58. Compliance Test/Measurement Load

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

VRX-DIFFp-p-MIN > 175 mV

0.4 UI = TRX-EYE-MIN

Silicon

+ Package

C = CTX

R = 50

D+ Package

D– Package

D+ Package

MPC8544EBVTARGA 数据表(PDF) 80 Page - NXP Semiconductors

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