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MPC8544EBVTARGA 数据表(PDF) 83 Page - NXP Semiconductors

部件名 MPC8544EBVTARGA
功能描述  MPC8544E PowerQUICC III Integrated Processor Hardware Specifications
PDF  117 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MPC8544EBVTARGA 数据表(HTML) 83 Page - NXP Semiconductors

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
83
Package Description
18.3
Pinout Listings
Table 62 provides the pinout listing for the MPC8544E 783 FC-PBGA package.
NOTE
The naming convention of TSEC1 and TSEC3 is used to allow the splitting
voltage rails for the eTSEC blocks and to ease the port of existing
PowerQUICC III software.
NOTE
The DMA_DACK[0:1] and TEST_SEL pins must be set to a proper state
during POR configuration. Please refer to Table 62 for more details.
Table 62. MPC8544E Pinout Listing
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
PCI
PCI1_AD[31:0]
AE8, AD8, AF8, AH12, AG12, AB9, AC9, AE9,
AD10, AE10, AC11, AB11, AB12, AC12, AF12,
AE11, Y14, AE15, AC15, AB15, AA15, AD16,
Y15, AB16, AF18, AE18, AC17, AE19, AD19,
AB17, AB18, AA16
I/O
OVDD
—
PCI1_C_BE[3:0]
AC10, AE12, AA14, AD17
I/O
OVDD
—
PCI1_GNT[4:1]
AE7, AG11,AH11, AC8
O
OVDD
4, 8, 24
PCI1_GNT0
AE6
I/O
OVDD
—
PCI1_IRDY
AF13
I/O
OVDD
2
PCI1_PAR
AB14
I/O
OVDD
—
PCI1_PERR
AE14
I/O
OVDD
2
PCI1_SERR
AC14
I/O
OVDD
2
PCI1_STOP
AA13
I/O
OVDD
2
PCI1_TRDY
AD13
I/O
OVDD
2
PCI1_REQ[4:1]
AF9, AG10, AH10, AD6
I
OVDD
—
PCI1_REQ0
AB8
I/O
OVDD
—
PCI1_CLK
AH26
I
OVDD
—
PCI1_DEVSEL
AC13
I/O
OVDD
2
PCI1_FRAME
AD12
I/O
OVDD
2
PCI1_IDSEL
AG6
I
OVDD
—



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