PCF85363ATLSLASHAX datasheet(37/86 Pages) NXP

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I2C-bus

7.10 Oscillator register

Bit

Symbol

CLKIV

OFFM

12_24

LOWJ

OSCD[1:0]

CL[1:0]

Section

Section 7.16

Section 7.8

Section 7.10.3

Section 7.10.4

Section 7.10.5

Section 7.10.6

Table 29. Oscillator - oscillator control register (address 25h) bit description

7.10.1 CLKIV: invert the clock output

Bit

Symbol

Value

Description

output clock inversion

0[1]

non-inverting; LOWJ mode will affect rising

edge

CLKIV

inverted; LOWJ mode will affect falling edge

Table 30. CLKIV bit - oscillator control register (address 25h)

[1]

Default value.

The clock selected with the COF[2:0] bits (register Function, address 28h) can be

inverted. This is intended for use in conjunction with the low jitter mode, LOWJ. The low

jitter mode reduces the jitter for the rising edge of the output clock. If the reduced jitter

needs to be on the falling edge, for example when using an open-drain clock output, then

the CLKIV bit can be used to implement this.

7.10.2 OFFM: offset calibration mode

See Section 7.8 for a full description of offset calibration.

7.10.3 12_24: 12 hour or 24 hour clock

Bit

Symbol

Value

Description

12 hour or 24 hour mode

0[1]

24 hour mode is selected

12_24

12 hour mode is selected

Table 31. 12_24 bit - oscillator control register (address 25h)

[1]

Default value.

In RTC mode, time counting can be configured for 24 hour clock or 12 hour clock with the

AMPM flag.

This bit is ignored in stop-watch mode.

7.10.4 LOWJ: low jitter mode

Bit

Symbol

Value

Description

LOWJ

low jitter CLK output bit

Table 32. LOWJ bit - oscillator control register (address 25h)

PCF85363A

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Product data sheet

Rev. 3.1 — 18 June 2021

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