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PCF85363ATL/AX 数据表(PDF) 40 Page - NXP Semiconductors |
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PCF85363ATL/AX 数据表(HTML) 40 Page - NXP Semiconductors |
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40 / 86 page  NXP Semiconductors PCF85363A Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input, and I2C-bus [1] Default value. The battery switch circuit may be disabled when not used. This disables all the circuit and save power consumption. When disabled connect VBAT and VDD together. 7.11.2 BSRR: battery switch internal refresh rate Bit Symbol Value Description battery switch refresh rate 0[1] low 3 BSRR 1 high Table 38. BSRR bit - battery switch control (address 26h) bit description [1] Default value. Non-user bit. Recommended to leave set at default. 7.11.3 BSM[1:0]: battery switch mode Bit Symbol Value Description battery switch mode bits 00[1] switching at the Vth level 01 switching at the VBAT level 10 switching at the higher level of Vth or VBAT 2 to 1 BSM[1:0] 11 switching at the lower level of Vth or VBAT Table 39. BSM[1:0] bits - battery switch control (address 26h) bit description [1] Default value. Switching is automatic and controlled by the voltages on the VBAT and VDD pins. There are three modes: • Compare VDD with an internal reference (Vth) • Compare VDD with VBAT • Compare VDD with an internal reference (Vth) and VBAT The last mode is useful when a rechargeable battery is employed. BSM[1:0] Condition Internal power VDD > Vth VDD 00 VDD < Vth VBAT VDD > VBAT VDD 01 VDD < VBAT VBAT VDD > the higher of Vth or VBAT VDD 10 VDD < the higher of Vth or VBAT VBAT VDD > the lower of Vth or VBAT VDD 11 VDD < the lower of Vth or VBAT VBAT Table 40. Battery switch-over modes PCF85363A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.1 — 18 June 2021 40 / 86 |
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