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数据搜索系统，热门电子元器件搜索 |
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AD9540PCB 数据表(PDF) 4 Page - Analog Devices |
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AD9540PCB 数据表(HTML) 4 Page - Analog Devices |
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4 / 32 page  AD9540 Rev. 0 | Page 4 of 32 SPECIFICATIONS AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ TA = 25°C), DAC_RSET = 3.92 kΩ, CP_RSET = 3.09 kΩ, DRV_RSET = 4.02 kΩ, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments TOTAL SYSTEM JITTER AND PHASE NOISE FOR 105 MHz ADC CLOCK GENERATION CIRCUIT Converter Limiting Jitter1 720 fS rms Resultant SNR 59.07 dB Phase Noise of Fundamental @ 10 Hz Offset 80 dBc/Hz @ 100 Hz Offset 92 dBc/Hz @ 1 kHz Offset 101 dBc/Hz @ 10 kHz Offset 110 dBc/Hz @ 100 kHz Offset 147 dBc/Hz ≥1 MHz Offset 153 dBc/Hz TOTAL SYSTEM PHASE NOISE FOR 210 MHz ADC CLOCK GENERATION CIRCUIT Phase Noise of Fundamental @ 10 Hz Offset 79.2 dBc/Hz @ 100 Hz Offset 86 dBc/Hz @ 1 kHz Offset 95 dBc/Hz @ 10 kHz Offset 105 dBc/Hz @ 100 kHz Offset 144 dBc/Hz @ 1 MHz Offset 151 dBc/Hz TOTAL SYSTEM TIME JITTER FOR CLOCKS 155.52 MHz Clock 581 fS rms 12 kHz to 1.3 MHz bandwidth 622.08 MHz Clock 188 fS rms 12 kHz to 5 MHz bandwidth RF DIVIDER/CML DRIVER EQUIVALENT INTRINSIC TIME JITTER FIN = 414.72 MHz, FOUT = 51.84 MHz 136 fS rms R = 8, BW = 12 kHz to 400 kHz FIN = 1244.16 MHz, FOUT = 155.52 MHz 101 fS rms R = 8, BW = 12 kHz to 1.3 MHz FIN = 2488.32 MHz, FOUT = 622.08 MHz 108 fS rms R = 4, BW = 12 kHz to 5 MHz RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE FIN = 81.92 MHz, FOUT = 10.24 MHz RF Divider R = 8 @ 10 Hz 120 dBc/Hz @ 100 Hz 128 dBc/Hz @ 1 kHz 137 dBc/Hz @ 10 kHz 145 dBc/Hz @ 100 kHz 150 dBc/Hz ≥1 MHz 153 dBc/Hz FIN = 983.04 MHz, FOUT = 122.88 MHz RF Divider R = 8 @ 10 Hz 115 dBc/Hz @ 100 Hz 125 dBc/Hz @ 1 KHz 132 dBc/Hz @ 10 kHz 142 dBc/Hz @ 100 kHz 146 dBc/Hz @ 1 MHz 151 dBc/Hz >3 MHz 153 dBc/Hz |
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