AD9540PCB datasheet(21/32 Pages) AD

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AD9540

Rev. 0 | Page 21 of 32

MODES OF OPERATION

SELECTABLE CLOCK FREQUENCIES AND SELECT-

ABLE EDGE DELAY

Because the precision driver is implemented using a DDS, it

is possible to store multiple clock frequency words to enable

externally switchable clock frequencies. The phase accumulator

runs at a fixed frequency, according to the active profile’s clock

frequency word. Likewise, any delay applied to the rising and

falling edges is a static value that comes from the delay shift

word of the active profile. The device has eight different

phase/frequency profiles, each with its own 48-bit clock fre-

quency word and 14-bit delay shift word. Profiles are selected by

applying their digital value on the clock select (S0, S1, and S2)

pins. It is not possible to use the phase offset of one profile and

the frequency tuning word of another.

SYNCHRONIZATION MODES FOR MULTIPLE DEVICES

In a DDS system, the SYNC_CLK is derived internally from the

master system clock, SYSCLK, with a ÷4 divider. Because the

divider does not power up to a known state, multiple devices

in a system might have staggered clock phase relationships,

because each device can potentially generate the SYNC_CLK

rising edge from any one of four rising edges of SYSCLK. This

ambiguity can be resolved by employing digital synchronization

logic to control the phase relationships of the derived clocks

among different devices in the system. Note that the synchroni-

zation functions included on the AD9540 control only the

timing relationships among different digital clocks. They do not

compensate for the analog timing delay on the system clock due

to mismatched phase relationships on the input clock, CLK1

(see Figure 35).

SYSCLK DUT1

SYNC CLK

DUT1

SYNC CLK DUT2 w/o

SYNC_CLK ALIGNED

SYSCLK DUT2

SYNC CLK DUT2 w/

SYNC_CLK ALIGNED

SYNCHRONIZATION FUNCTIONS CAN ALIGN

DIGITAL CLOCK RELATIONSHIPS, THEY

CANNOT DESKEW THE EDGES OF CLOCKS

Figure 35. Synchronization Functions: Capabilities and Limitations

Automatic Synchronization

In automatic synchronization mode, the device is placed in slave

mode and automatically aligns the internal SYNC_CLK to a

master SYNC_CLK signal, supplied on the SYNC_IN input.

When this bit is enabled, the STATUS is not available as an

output; however, an out-of-lock condition can be detected by

reading Control Function Register 1 and checking the status of

the STATUS_Error bit. The automatic synchronization function

is enabled by setting the Control Function Register 1 automatic

synchronization bit, CFR1<3>. To employ this function at

higher clock rates (SYNC_CLK > 62.5 MHz, SYSCLK >

250 MHz), the high speed sync enable bit (CFR1<0>) should be

set as well.

Manual Synchronization, Hardware Controlled

In this mode, the user controls the timing relationship of the

SYNC_CLK with respect to SYSCLK. When hardware manual

synchronization is enabled, the SYNC_IN/ STATUS pin

becomes a digital input. For each rising edge detected on the

SYNC_IN input, the device advances the SYNC_IN rising edge

by one SYSCLK period. When this bit is enabled, the STATUS is

not available as an output; however, an out-of-lock condition

can be detected by reading Control Function Register 1 and

checking the status of the STATUS_Error bit. This synchro-

nization function is enabled by setting the hardware manual

synchronization enable bit, CFR1<1>.

Manual Synchronization, Software Controlled

In this mode, the user controls the timing relationship between

SYNC_CLK and SYSCLK through software programming.

When the software manual synchronization bit (CFR1<2>) is

set high, the SYNC_CLK is advanced by one SYSCLK cycle.

Once this operation is complete, the bit is cleared. The user can

set this bit repeatedly to advance the SYNC_CLK rising edge

multiple times. Because the operation does not use the

SYNC_IN/ STATUS pin as a SYNC_IN input, the STATUS sig-

nal can be monitored on the STATUS pin during this operation.

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