数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

AD9540PCB 数据表(PDF) 24 Page - Analog Devices

部件名 AD9540PCB
功能描述  655 MHz Low Jitter Clock Generator
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9540PCB 数据表(HTML) 24 Page - Analog Devices

Back Button AD9540PCB Datasheet HTML 20Page - Analog Devices AD9540PCB Datasheet HTML 21Page - Analog Devices AD9540PCB Datasheet HTML 22Page - Analog Devices AD9540PCB Datasheet HTML 23Page - Analog Devices AD9540PCB Datasheet HTML 24Page - Analog Devices AD9540PCB Datasheet HTML 25Page - Analog Devices AD9540PCB Datasheet HTML 26Page - Analog Devices AD9540PCB Datasheet HTML 27Page - Analog Devices AD9540PCB Datasheet HTML 28Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 32 page
background image
AD9540
Rev. 0 | Page 24 of 32
REGISTER MAP AND DESCRIPTION
Table 5. Register Map
Register
Name (Serial
Address)
Bit
Range
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value/
Profile
<31:24>
Open1
Open1
Open1
Open1
Open1
Open1
Open1
STATUS_Error
0x00
<23:16>
LOAD SRR @
I/O_UPDATE
Auto-
Clear
Freq.
Accum.
Auto-
Clear
Phase
Accum.
Enable
Sine Out-
put
Clear
Freq.
Accum.
Clear
Phase
Accum.
Open1
Open1
0x00
<15:8>
LSB First
SDI/O
Input
Only
Open1
Open1
Open1
Open1
Open1
Open1
0x00
Control
Function
Register 1
(CFR1) (0x00)
<7:0>
Dig. Power-
Down
PFD
Input
Power-
Down
REFIN
Cyrstal
Enable
SYNC_CLK
Out Dis-
able
Auto
Sync
Multiple
AD9540s
Software
Manual
Sync
Hardware
Manual
Sync
High Speed
Sync Enable
0x00
<39:32>
DAC Power-
Down
Open1
Open1
Open1
Open1
Open1
Internal
Band Gap
Power-
Down
Internal CML
Driver
DRV_RSET
0x00
<31:24>
Clock Driver Rising Edge <31:29>
Clock Driver Falling Edge Control
<28:26>
PLL Lock
Detect
Enable
PLL Lock
Detect Mode
0x00
<23:16>
RF Divider
Power-
Down
RF Divider Ratio
<22:21>
Clock
Driver
Power-
Down
Clock Driver Input
Select <19:18>
Slew Rate
Control
RF Div CLK1
Mux Bit
0x78
<15:8>
Divider M Control <15:12>
Divider N Control <11:8>
0x00
Control
Function
Register 2
(CFR2) (0x01)
<7:0>
Open1
Open1
CP
Polarity
CP Full PD
CP Quick
PD
CP Current Scale <2:0>
0x07
<23:16>
Rising Delta Frequency Tuning Word <23:16>
0x00
<15:8>
Rising Delta Frequency Tuning Word <15:8>
0x00
Rising Delta
Frequency
Tuning Word
(RDFTW)
(0x02)
<7:0>
Rising Delta Frequency Tuning Word <7:0>
0x00
<23:16>
Falling Delta Frequency Tuning Word <23:16>
0x00
<15:8>
Falling Delta Frequency Tuning Word <15:8>
0x00
Falling Delta
Frequency
Tuning Word
(FDFTW)
(0x03)
<7:0>
Falling Delta Frequency Tuning Word <7:0>
0x00
<15:8>
Rising Sweep Ramp Rate <15:8>
0x00
Rising Sweep
Ramp Rate
(RSRR) (0x04)
<7:0>
Rising Sweep Ramp Rate <7:0>
0x00
<15:8>
Rising Sweep Ramp Rate <15:8>
0x00
Falling Sweep
Ramp Rate
(FSRR) (0x05)
<7:0>
Rising Sweep Ramp Rate <7:0>
0x00
1 In all cases, Open bits must be written to 0.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com