655 MHz Low Jitter Clock Generator

AD9540

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

© 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Excellent intrinsic jitter performance

25 Mb/s write-speed serial I/O control

200 MHz phase frequency detector inputs

655 MHz programmable input dividers for the phase fre-

quency detector (÷M, ÷N) {M, N = 1..16} (bypassable)

Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)

8 programmable internal clock rates

1.8 V supply for device operation

3.3 V supply for I/O, CML driver, and charge pump output

Software controlled power-down

48-lead LFCSP package

Programmable charge pump current (up to 4 mA)

Multichip synchronization

Dual-mode PLL lock detect

655 MHz CML-mode PECL-compliant driver

APPLICATIONS

Clocking high performance data converters

Base station clocking applications

Network (SONET/SDH) clocking

Gigabit Ethernet (GbE) clocking

Instrumentation clocking circuits

FUNCTIONAL BLOCK DIAGRAM

AVDD AGND DVDD DGND VCML

VCP

CP_RSET

CP

REF, AMP

REFIN

REFIN

CLK1

CLK1

CHARGE

PUMP

PHASE

FREQUENCY

DETECTOR

M DIVIDER

N DIVIDER

DIVIDER

1, 2, 4, 8

SYNC_IN/STATUS

SYNC, PLL

LOCK

SCLK

SDI/O

SDO

CS

SERIAL

CONTROL

PORT

TIMING AND

CONTROL LOGIC

CLK2

CP

CLK2

DRV_RSET

OUT0

CML

OUT0

VCML

CLK

DIVCLK

S2

S1

S0

PHASE/

FREQUENCY

PROFILES

DDS

IOUT

IOUT

DAC

DAC_RSET

48

10

14

Figure 1.