AD9540PCB datasheet(30/32 Pages) AD

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AD9540

Rev. 0 | Page 30 of 32

CFR2<24> = 0 (default). The lock detect acts as a status indica-

tor (PLL is locked 0 or unlocked 1).

CFR2<24> = 1. The lock detect acts as a lead-lag indicator. A 1

on the STATUS pin means that the CLK2 pin lags the

reference. A 0 means that the CLK2 pin leads the reference.

CFR2<23> RF Divider Power-Down

This bit powers down the RF divider to save power when

not in use.

CFR2<23> = 0 (default). The RF divider is on.

CFR2<23> = 1. The RF divider is powered down and an alter-

nate path between the CLK1 inputs and SYSCLK is enabled.

CFR2<22:21> RF Divider Ratio

These two bits control the RF divider ratio (÷R).

CFR2<22:21> = 11 (default). RF Divider R = 8.

CFR2<22:21> = 10. RF Divider R = 4.

CFR2<22:21> = 01. RF Divider R = 2.

CFR2<22:21> = 00. RF Divider R = 1. Note that this is not the

same as bypassing the RF divider.

CFR2<20> Clock Driver Power-Down

This bit powers down the CML clock driver circuit.

CFR2<20> =1 (default). The CML clock driver circuit is

powered down.

CFR2<20> = 0. The CML clock driver is powered up.

CFR2<19:18> Clock Driver Input Select

These bits control the mux on the input for the CML clock

driver.

CFR2<19:18> = 00. The CML clock driver is disconnected from

all inputs (and does not toggle).

CFR2<19:18> = 01. The CML clock driver is driven by the

CLK2 input pin.

CFR2<19:18> = 10 (default). The CML clock driver is driven by

the output of the RF divider.

CFR2<19:18> = 11. The CML clock driver is driven by the input

of the RF divider

CFR2<17> Slew Rate Control Bit

Even without the additional surge current supplied by the rising

edge slew rate control bits and the falling edge slew rate control

bits, the device applies a default 7.6 mA surge current to the

rising edge and a 4.05 mA surge current to the falling edge. This

bit disables all slew rate enhancement surge current, including

the default values.

CFR2<17> = 0 (default). The CML driver applies default surge

current to rising and falling edges.

CFR2<17> = 1. Driver applies no surge current during

transitions. The only current is the continuous current.

CFR2<16> RF Divider CLK1 Mux

This bit toggles the mux to control whether the RF divider out-

put or input is supplying SYSCLK to the device.

CFR2<16> = 0 (default). The RF divider output supplies the

DDS SYSCLK.

CFR2<16> = 1. The RF divider input supplies the DDS SYSCLK

(bypass the divider). Note that regardless of the condition of the

configuration of the clock input, the DDS SYSCLK must not

exceed the maximum rated clock speed.

CFR2<15:12> REFIN Divider (÷M) Control Bits

These four bits set the REFIN divider (÷M) ratio where M is a

value = 1 to 16 and CFR2<15:12> = 0000 means that M = 1 and

CFR2<15:12> = 1111 means that M = 16 or simply, M =

CFR2<15:12> + 1.

Table 8. REFIN Divider Values (÷M)

CFR2<15:12> =

M =

CFR2<15:12> =

M =

0000

1000

0001

1001

0010

1010

0011

1011

0100

1100

0101

1101

0110

1110

0111

1111

CFR2<11:8> CLK2 Divider (÷N) Control Bits

These 4 bits set the CLK2 divider (÷N) ratio where N is a value

= 1 to 16 and CFR2<11:8> = 0000 means that N = 1 and

CFR2<11:8> = 1111 means that N = 16 or N = CFR2<11:8> + 1.

Table 9. CLK2 Input Divider Values (÷N)

CFR2<15:12> =

N =

CFR2<11:8> =

N =

0000

1000

0001

1001

0010

1010

0011

1011

0100

1100

0101

1101

0110

1110

0111

1111

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