AD9540PCB datasheet(22/32 Pages) AD

22 / 32 page

AD9540

Rev. 0 | Page 22 of 32

SERIAL PORT OPERATION

An AD9540 serial data-port communication cycle has two

phases. Phase 1 is the instruction cycle, which is the writing of

an instruction byte to the AD9540, coincident with the first

eight SCLK rising edges. The instruction byte provides the

AD9540 serial port controller with information regarding the

data transfer cycle, which is Phase 2 of the communication cycle.

The Phase 1 instruction byte defines whether the upcoming data

transfer is read or write and the serial address of the

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9540. The

remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9540

and the system controller. The number of bytes transferred

during Phase 2 of the communication cycle is a function of the

Function Register 2, which is four bytes wide, Phase 2 requires that

four bytes be transferred. If accessing a frequency tuning word,

which is six bytes wide, Phase 2 requires that six bytes be trans-

ferred. After transferring all data bytes per the instruction, the

communication cycle is completed.

At the completion of any communication cycle, the AD9540

serial port controller expects the next eight rising SCLK edges

to be the instruction byte of the next communication cycle. All

data input to the AD9540 is registered on the rising edge of

SCLK. All data is driven out of the AD9540 on the falling edge

of SCLK. Figure 36 through Figure 39 are useful in understand-

ing the general operation of the AD9540 serial port.

INSTRUCTION CYCLE

SCLK

SDI/O

DATA TRANSFER CYCLE

Figure 36. Serial Port Write Timing—Clock Stall Low

DON'T CARE

INSTRUCTION CYCLE

SCLK

SDI/O

DATA TRANSFER CYCLE

DO 5 DO 4 DO 3 DO 2 DO 1

DO 0

DO 7

DO 6

SDO

Figure 37. 3-Wire Serial Port Read Timing—Clock Stall Low

INSTRUCTION CYCLE

SCLK

SDI/O

DATA TRANSFER CYCLE

Figure 38. Serial Port Write Timing−Clock Stall High

DO 5 DO 4 DO 3 DO 2 DO 1 DO 0

DO 7 DO 6

INSTRUCTION CYCLE

SCLK

SDI/O

DATA TRANSFER CYCLE

Figure 39. 2-Wire Serial Port Read Timing−Clock Stall High

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