AD9540PCB datasheet(8/32 Pages) AD

8 / 32 page

AD9540

Rev. 0 | Page 8 of 32

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

51.84 MHz FOUT

@ 10 Hz Offset

110

dBc/Hz

@ 100 Hz Offset

121

dBc/Hz

@ 1 kHz Offset

135

dBc/Hz

@ 10 kHz Offset

142

dBc/Hz

@ 100 kHz Offset

148

dBc/Hz

> 1 MHz Offset

153

dBc/Hz

105 MHz Analog Out

@ 10 Hz Offset

105

dBc/Hz

@ 100 Hz Offset

115

dBc/Hz

@ 1 kHz Offset

126

dBc/Hz

@ 10 kHz Offset

132

dBc/Hz

@ 100 kHz Offset

140

dBc/Hz

>1 MHz Offset

145

dBc/Hz

155.52 MHz Analog Out

@ 10 Hz Offset

100

dBc/Hz

@ 100 Hz Offset

112

dBc/Hz

@ 1 kHz Offset

123

dBc/Hz

@ 10 kHz Offset

131

dBc/Hz

@ 100 kHz Offset

138

dBc/Hz

>1 MHz Offset

144

dBc/Hz

1 The SNR of a 14-bit ADC was measured with an ENCODE rate of 105 MSPS and an AIN of 170 MHz. The resultant SNR was known to be limited by the jitter of the clock,

not by the noise on the AIN signal. From this SNR value, the jitter affecting the measurement can be back calculated.

2 Driving the PLLREF input buffer. The crystal oscillator section of this input stage performs up to only 30 MHz.

3 The charge pump output compliance range is functionally 0.2 V to (CPVDD − 0.2 V). The value listed here is the compliance range for 5% matching.

4 The input impedance of the CLK1 input is 1500 Ω. However, to provide matching on the clock line, an external 50 Ω load is used.

5 Measured as peak-to-peak between DAC outputs.

6 For a 4.02 kΩ resistor from DRV_RSET to GND.

7 IBIS models for the digital I/O pins available upon request.

8 Assumes a 1 mA load.

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