ST25DV64K datasheet(65/200 Pages) STMICROELECTRONICS

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6.1.2

Stop condition

Stop is identified by a rising edge of serial data (SDA) while the serial clock (SCL) is stable and driven high.

A Stop condition terminates communication between the device and the bus master. A Read command that

is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop

condition at the end of a Write command triggers the internal write cycle.

6.1.3

Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether a bus master or a

slave device, releases the serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the

receiver pulls the SDA low to acknowledge the receipt of the eight data bits.

6.1.4

Data input

During data input, the device samples serial data (SDA) on the rising edge of the serial clock (SCL). For correct

device operation, the SDA must be stable during the rising edge of the SCL, and the SDA signal must change

only when the SCL is driven low.

6.2

I2C timeout

During the execution of an I²C operation, RF communications are not possible.

To prevent RF communication freezing due to inadvertent indeterminate instructions sent to the I²C bus, the

ST25DVxxx features a timeout mechanism that automatically resets the I²C logic block.

6.2.1

I2C timeout on Start condition

I2C communication with the ST25DVxxx starts with a valid Start condition, followed by a device select code.

If the delay between the Start condition and the following rising edge of the serial clock (SCL) that samples the

most significant of the Device Select exceeds the tSTART_OUT time (see Table 248. I2C AC characteristics up to

85°C and Table 249. I2C AC characteristics up to 125°C), the I²C logic block is reset and further incoming data

transfer is ignored until the next valid Start condition.

Figure 25. I²C timeout on Start condition

SCL

SDA

tSTART_OUT

Start

condition

6.2.2

I2C timeout on clock period

During data transfer on the I²C bus, if the serial clock pulse width high (tCHCL) or serial clock pulse width low

(tCLCH) exceeds the maximum value specified in Table 248. I2C AC characteristics up to 85°C and Table 249. I2C

AC characteristics up to 125°C, the I²C logic block is reset and any further incoming data transfer is ignored until

the next valid Start condition.

ST25DV04K ST25DV16K ST25DV64K

I2C timeout

DS10925 - Rev 9

page 65/200

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