ST25DV64K datasheet(69/200 Pages) STMICROELECTRONICS

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6.4.3

Minimizing system delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from

its internal latches to the memory cells. The maximum I²C write time (tw) is shown in Table 248. I2C AC

characteristics up to 85°C and Table 249. I2C AC characteristics up to 125°C, but the typical time is shorter.

To make use of this, a polling sequence can be used by the bus master.

The sequence, as shown in Figure 28, is:

•

Initial condition: a write cycle is in progress.

•

Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new

instruction).

•

Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus master goes back

to Step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the

device is ready to receive the second part of the instruction (the first byte of this instruction having been sent

during Step 1).

Note:

There is no need of polling when writing in dynamic registers or in mailbox, since programming time is null.

Figure 28. Write cycle polling flowchart using ACK

Write cycle

in progress

Operation is

addressing the

memory

Start condition

Device select

with RW = 0

ACK

returned

YES

Stop

Data for the

Write operation

Send Address

and Receive ACK

YES

StartCondition

Continue the

Write operation

Continue the

Random Read operation

Device select

with RW = 1

First byte of instruction

with RW = 0 already

decoded by the device

ST25DV04K ST25DV16K ST25DV64K

I2C Write operations

DS10925 - Rev 9

page 69/200

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