ST25DV64K datasheet(143/200 Pages) STMICROELECTRONICS

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Test conditions specified in Table 243. I2C operating conditions

Symbol

Alt.

Parameter

Min.

Max.

Unit

tCLQV (6)

tAA

Clock low to next data valid (access time)

450

tCHDX (7)

tSU:STA

Start condition set up time

250

tDLCL

tHD:STA

Start condition hold time

0.25

35000 (8)

µs

tCHDH

tSU:STO

Stop condition set up time

250

tDHDL

tBUF

Time between Stop condition and next Start

condition

500

I²C write time (9)

tbootDC

RF OFF and LPD = 0

0.6

tbootLPD

RF OFF

0.6

1. tCHCL timeout.

2. tCLCH timeout.

3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the

I2C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.

4. Characterized on bench.

5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a

compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus ×

Cbus time constant is less than 150 ns (as specified in the Figure 76. I2C Fast mode (fC = 1 MHz): maximum

Rbus value versus bus parasitic capacitance (Cbus)).

7. For a reStart condition, or following a write cycle.

8. tDLCL timeout.

9. I2C write time for 1 Byte, 2 Bytes, 3 Bytes or 4 Bytes in EEPROM (user memory and system configuration),

provided they are all located in the same memory page, that is the most significant memory address bits

(b16-b2) are the same.

Table 249. I2C AC characteristics up to 125°C

Test conditions specified in Table 243. I2C operating conditions

Symbol

Alt.

Parameter

Min.

Max.

Unit

fSCL

Clock frequency

0.05

1000

kHz

tCHCL

tHIGH

Clock pulse width high

0.26

25000 (1)

µs

tCLCH

tLOW

Clock pulse width low

0.5

25000 (2)

µs

tSTART_OUT

I²C timeout on Start condition

tXH1XH2

Input signal rise time

(3)

tXL1XL2

Input signal fall time

(3)

tDL1DL2 (4)

SDA (out) fall time

120

tDXCX

tSU:DAT

Data in set up time

tCLDX

tHD:DAT

Data in hold time

tCLQX (5)

tDH

Data out hold time

100

tCLQV (6)

tAA

Clock low to next data valid (access time)

450

tCHDX (7)

tSU:STA

Start condition set up time

250

ST25DV04K ST25DV16K ST25DV64K

I2C DC and AC parameters

DS10925 - Rev 9

page 143/200

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