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ST25DV64K 数据表(PDF) 177 Page - STMicroelectronics |
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ST25DV64K 数据表(HTML) 177 Page - STMicroelectronics |
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177 / 200 page  Table 292. Sequential read in Dynamic register and mailbox continuously if fast transfer mode is activated Request/Response Frame Comment Master drives SDA Slave drives SDA Start A6h - Device select for writing - ACK 9th bit 20h - Send Address MSB (1 Byte) - ACK 9th bit Dynamic Register ADDRESS_LSB - Send Address LSB (1 Byte) Dynamic register are located from address 2000h to 2007h - ACK 9th bit Start A7h - Device select for reading - ACK 9th bit - DATA 0 Receive Data 0 ACK - 9th bit - DATA 1 Receive Data 1 ACK - 9th bit - ... ... ... - ... - DATA n Receive Data n (n ≤ 8) Last Dynamic register address 2007h ACK - 9th bit - DATA n + 1 Mailbox byte 0 ACK - 9th bit - DATA n + 2 Mailbox byte 1 ACK - 9th bit - ... ... ... - ... - Data n + i Mailbox byte i (i < 256) NO_ACK - 9th bit Stop - End of reading ST25DV04K ST25DV16K ST25DV64K I2C sequential read DS10925 - Rev 9 page 177/200 |
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