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ST25DV64K 数据表(PDF) 183 Page - STMicroelectronics |
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ST25DV64K 数据表(HTML) 183 Page - STMicroelectronics |
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183 / 200 page  Revision history Table 298. Document revision history Date Revision Changes 23-Feb-2017 1 Initial release. 20-Sep-2017 2 Updated: • Features • Section 4 Memory management • Section 5 ST25DVxxx specific features • Section 5.6.4 System memory protection • Section 6.4.2 I2C Sequential write • Section 6 I2C operation • Section 7 RF operations • Section 9.1 Maximum rating • Table 158. Get System Info response format Error_flag is NOT set • Table 242. Absolute maximum ratings • Table 244. AC test measurement conditions • Table 246. I2C DC characteristics up to 85°C • Table 248. I2C AC characteristics up to 85°C • Table 250. GPO DC characteristics up to 85°C • Table 253. RF characteristics • Table 254. Operating conditions • Table 256. TSSOP8 – Mechanical data • Table 261. Ordering information scheme • Figure 30. I2C Present Password Sequence • Figure 31. I2C Write Password Sequence • Figure 80. TSSOP8 – Outline Added: • Table 159. Memory size • Table 243. I2C operating conditions • Table 247. I2C DC characteristics up to 125°C • Table 249. I2C AC characteristics up to 125°C • Table 251. GPO DC characteristics up to 125°C 04-Oct-2017 3 Updated: • Features • Section 10 Package information Added: • NFC certified logo 19-Dec-2017 4 Added: • Figure 4. ST25DVxxx 10-ball WLCSP package connections with Cmos interrupt output (GPO) • Section 10.5 WLCSP10 package information • Table 259. WLCSP - 10 balls, 1.649x1.483 mm, 0.4 mm pitch, wafer level chip scale mechanical data • Figure 84. WLCSP - 10 balls, 1.649x1.483 mm, 0.4 mm pitch, wafer level chip scale package outline • Figure 85. WLCSP - 10 balls, 1.649x1.483 mm, 0.4 mm pitch, wafer level chip scale recommended footprint Updated: • Features • Section 1 Description ST25DV04K ST25DV16K ST25DV64K DS10925 - Rev 9 page 183/200 |
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