M76DW52003BA datasheet(7/27 Pages) STMICROELECTRONICS

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M76DW52003TA, M76DW52003BA

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance.

Byte/Word Organization Select (BYTE). The

Byte/Word Organization Select pin is used to

switch between the x8 and x16 Bus modes of the

Flash memory. When Byte/Word Organization Se-

lect is Low, VIL, the Flash memory is in x8 mode,

when it is High, VIH, the Flash memory is in x16

mode.

SRAM Chip Enable (E1S, E2S). The Chip En-

able inputs activate the SRAM memory control

logic, input buffers and decoders. E1S at VIH or

E2S at VIL deselects the memory and reduces the

power consumption to the standby level. E1S and

E2S can also be used to control writing to the

SRAM memory array, while W remains at VIL. It is

not allowed to set EF at VIL, E1S at VIL and E2S at

VIH at the same time.

SRAM Upper Byte Enable (UBS). The

Upper

Byte Enable enables the upper bytes for SRAM

(DQ8-DQ15). UBS is active low.

SRAM Lower Byte Enable (LBS). The

Lower

Byte Enable enables the lower bytes for SRAM

(DQ0-DQ7). LBS is active low.

VCCF Supply Voltage (2.7V to 3.3V). VCCF pro-

vides the power supply to the internal core of the

Flash Memory device. It is the main power supply

for all operations (Read, Program and Erase).

VCCS Supply Voltage (2.7V to 3.3V). VCCS pro-

vides the power supply for the SRAM control pins.

VSS Ground. VSS is the ground reference for all

voltage measurements in the Flash and SRAM

chips.

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