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PPC5604BAMLL4R 数据表(PDF) 35 Page - NXP Semiconductors |
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PPC5604BAMLL4R 数据表(HTML) 35 Page - NXP Semiconductors |
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35 / 109 page  Package pinouts and signal descriptions MPC5604B/C Microcontroller Data Sheet, Rev. 15 NXP Semiconductors 35 Table 13. Recommended operating conditions (5.0 V) Symbol Parameter Conditions Value Unit Min Max VSS SR Digital ground on VSS_HV pins — 0 0 V VDD 1 SR Voltage on VDD_HV pins with respect to ground (VSS) —4.5 5.5 V Voltage drop2 3.0 5.5 VSS_LV 3 SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) —VSS−0.1 VSS+0.1 V VDD_BV 4 SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) —4.5 5.5 V Voltage drop2 3.0 5.5 Relative to VDD VDD−0.1 VDD+0.1 VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS —VSS−0.1 VSS+0.1 V VDD_ADC 5 SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) —4.5 5.5 V Voltage drop2 3.0 5.5 Relative to VDD VDD−0.1 VDD+0.1 VIN SR Voltage on any GPIO pin with respect to ground (VSS) —VSS−0.1 — V Relative to VDD —VDD+0.1 IINJPAD SR Injected input current on any pin during overload condition — −55 mA IINJSUM SR Absolute sum of all injected input currents during overload condition — −50 50 TVDD SR VDD slope to ensure correct power up 6 —3.07 0.25 V/µs V/s TA C-Grade Part SR Ambient temperature under bias fCPU ≤ 64 MHz −40 85 °C TJ C-Grade Part SR Junction temperature under bias −40 110 TA V-Grade Part SR Ambient temperature under bias −40 105 TJ V-Grade Part SR Junction temperature under bias −40 130 TA M-Grade Part SR Ambient temperature under bias −40 125 TJ M-Grade Part SR Junction temperature under bias −40 150 1 100 nF capacitance needs to be provided between each V DD/VSS pair. 2 Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 3 330 nF capacitance needs to be provided between each V DD_LV/VSS_LV supply pair. 4 100 nF capacitance needs to be provided between V DD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 5 1 µF (electrolithic/tantalum) + 47 nF (ceramic) capacitance needs to be provided between V DD_ADC/VSS_ADC pair. Another ceramic cap of 10 nF with low inductance package can be added. 6 Guaranteed by device validation. 7 Minimum value of TV DD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH). |
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