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PPC5604BAMLL4R 数据表(PDF) 80 Page - NXP Semiconductors |
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PPC5604BAMLL4R 数据表(HTML) 80 Page - NXP Semiconductors |
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80 / 109 page  MPC5604B/C Microcontroller Data Sheet, Rev. 15 Package pinouts and signal descriptions NXP Semiconductors 80 2.27.2 DSPI characteristics Table 46. DSPI characteristics1 1 Operating conditions: C L = 10 to 50 pF, SlewIN = 3.5 to 15 ns. No. Symbol C Parameter DSPI0/DSPI1 DSPI2 Unit Min Typ Max Min Typ Max 1tSCK SR D SCK cycle time Master mode (MTFE = 0) 125 — — 333 — — ns DSlave mode (MTFE = 0) 125 — — 333 — — D Master mode (MTFE = 1) 83 — — 125 — — DSlave mode (MTFE = 1) 83 — — 125 — — —fDSPI SR D DSPI digital controller frequency — — fCPU —— fCPU MHz — ΔtCSC CC D Internal delay between pad associated to SCK and pad associated to CSn in master mode for CSn1 →0 Master mode — — 1302 2 Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK starts before CSn is asserted. DSPI2 has only SLOW SCK available. —— 153 ns — ΔtASC CC D Internal delay between pad associated to SCK and pad associated to CSn in master mode for CSn1 →1 Master mode — — 1303 — — 1303 ns 2tCSCext 4 SR D CS to SCK delay Slave mode 32 — — 32 — — ns 3tASCext 5 SR D After SCK delay Slave mode 1/fDSPI + 5 — — 1/fDSPI + 5 — — ns 4tSDC CC D SCK duty cycle Master mode — tSCK/2 — — tSCK/2 — ns SR D Slave mode tSCK/2 — — tSCK/2 — — 5tA SR D Slave access time Slave mode — — 1/fDSPI + 70 — — 1/fDSPI + 130 ns 6tDI SR D Slave SOUT disable time Slave mode 7 — — 7 — — ns 7tPCSC SR D PCSx to PCSS time 0 — — 0 — — ns 8tPASC SR D PCSS to PCSx time 0 — — 0 — — ns 9tSUI SR D Data setup time for inputs Master mode 43 — — 145 — — ns Slave mode 5 — — 5 — — 10 tHI SR D Data hold time for inputs Master mode 0 — — 0 — — ns Slave mode 26 —— 26 —— 11 tSUO 7 CC D Data valid after SCK edge Master mode — — 32 — — 50 ns Slave mode — — 52 — — 160 12 tHO 7 CC D Data hold time for outputs Master mode 0 — — 0 — — ns Slave mode 8 — — 13 — — |
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