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PPC5604BAMLL4R 数据表(PDF) 1 Page - NXP Semiconductors |
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PPC5604BAMLL4R 数据表(HTML) 1 Page - NXP Semiconductors |
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1 / 109 page  NXP Semiconductors Data Sheet: Technical Data Document Number: MPC5604BC Rev. 15, 10/2021 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. MPC5604B/C 144 LQFP (20 x 20 x 1.4 mm) 100 LQFP (14 x 14 x 1.4 mm) 208 MAPBGA (17 x 17 x 1.7 mm) 64 LQFP (10 x 10 x 1.4 mm) Features • Single issue, 32-bit CPU core complex (e200z0) – Compliant with the Power Architecture® embedded category – Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. • Up to 512 KB on-chip code flash supported with the flash controller and ECC • 64 (4 × 16) KB on-chip data flash memory with ECC • Up to 48 KB on-chip SRAM with ECC • Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity • Interrupt controller (INTC) with 148 interrupt vectors, including 16 external interrupt sources and 18 external interrupt/wakeup sources • Frequency modulated phase-locked loop (FMPLL) • Crossbar switch architecture for concurrent access to peripherals, flash memory, or RAM from multiple bus masters • Boot assist module (BAM) supports internal flash programming via a serial link (CAN or SCI) • Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS-lite) • 10-bit analog-to-digital converter (ADC) • 3 serial peripheral interface (DSPI) modules • Up to 4 serial communication interface (LINFlex) modules • Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers • 1 inter IC communication interface (I2C) module • Up to 123 configurable general purpose pins supporting input and output operations (package dependent) • Real Time Counter (RTC) with clock source from128 kHz or 16 MHz internal RC oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds • Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution • 1 System Module Timer (STM) • Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard • Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) • On-chip voltage regulator (VREG) for regulation of input supply for all internal levels MPC5604B/C Microcontroller Data Sheet |
类似零件编号 - PPC5604BAMLL4R |
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类似说明 - PPC5604BAMLL4R |
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