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PPC5606BAVLL6R 数据表(PDF) 39 Page - NXP Semiconductors |
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PPC5606BAVLL6R 数据表(HTML) 39 Page - NXP Semiconductors |
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39 / 114 page  Electrical characteristics MPC5607B Microcontroller Data Sheet, Rev. 10 NXP Semiconductors 39 NOTE RAM data retention is guaranteed with VDD_LV not below 1.08 V. VSS_ADC SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (VSS) —VSS − 0.1 VSS +0.1 V VDD_ADC 5 SR Voltage on VDD_HV_ADC0, VDD_HV_ADC1 (ADC reference) with respect to ground (VSS) —4.5 5.5 V Voltage drop2 3.0 5.5 Relative to VDD VDD − 0.1 VDD +0.1 VIN SR Voltage on any GPIO pin with respect to ground (VSS) —VSS − 0.1 — V Relative to VDD —VDD +0.1 IINJPAD SR Injected input current on any pin during overload condition — −55 mA IINJSUM SR Absolute sum of all injected input currents during overload condition — −50 50 TVDD SR VDD slope to ensure correct power up 6 —3.07 0.25 V/µs V/s TA C-Grade Part SR Ambient temperature under bias fCPU ≤ 64 MHz8 −40 85 °C TJ C-Grade Part SR Junction temperature under bias — −40 110 TA V-Grade Part SR Ambient temperature under bias fCPU ≤ 64 MHz8 −40 105 TJ V-Grade Part SR Junction temperature under bias — −40 130 TA M-Grade Part SR Ambient temperature under bias fCPU ≤ 64 MHz8 −40 125 TJ M-Grade Part SR Junction temperature under bias — −40 150 1 100 nF capacitance needs to be provided between each V DD/VSS pair. 2 Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 3 330 nF capacitance needs to be provided between each V DD_LV/VSS_LV supply pair. 4 470 nF capacitance needs to be provided between V DD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). While the supply voltage ramps up, the slope on VDD_BV should be less than 0.9VDD_HV in order to ensure the device does not enter regulator bypass mode. 5 100 nF capacitance needs to be provided between V DD_ADC/VSS_ADC pair. 6 Guaranteed by device validation 7 Minimum value of TV DD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH) 8 When the FMPLL uses the frequency modulation with a modulation depth of 4% from the center spread frequency, the maximum value of fCPU is 66.56 MHz. Table 13. Recommended operating conditions (5.0 V) (continued) Symbol Parameter Conditions Value Unit Min Max |
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