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PPC5606BAVLL6R 数据表(PDF) 89 Page - NXP Semiconductors

部件名 PPC5606BAVLL6R
功能描述  MPC5607B Microcontroller Data Sheet
PDF  114 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PPC5606BAVLL6R 数据表(HTML) 89 Page - NXP Semiconductors

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10
tHI
SR D Data hold time for inputs
Master mode
0
0
ns
Slave mode
26
——
26
——
11
tSUO
7
CC D Data valid after SCK edge Master mode
32
50
ns
Slave mode
52
160
12
tHO
7
CC D Data hold time for outputs
Master mode
0
0
ns
Slave mode
8
13
1 Operating conditions: C
L = 10 to 50 pF, SlewIN = 3.5 to 15 ns
2 Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK
starts before CSn is asserted. DSPI2 has only SLOW SCK available.
3 Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is
deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.
4 The t
CSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay
between internal CS and internal SCK must be higher than
ΔtCSC to ensure positive tCSCext.
5 The t
ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between
internal CS and internal SCK must be higher than
ΔtASC to ensure positive tASCext.
6 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
7 SCK and SOUT are configured as MEDIUM pad.
Table 47. DSPI characteristics1 (continued)
No.
Symbol
C
Parameter
DSPI0/DSPI1/DSPI3/DSPI5
DSPI2/DSPI4
Unit
Min
Typ
Max
Min
Typ
Max



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