AX88872P datasheet(2/36 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

CONFIDENTIAL

AX88872P Swipeater Controller

PRELIMINARY

CONTENTS

1.0 AX88872 OVERVIEW ....................................................................................................................................... 4

1.1 GENERAL DESCRIPTION...................................................................................................................................... 4

1.2 AX88872 BLOCK DIAGRAM: .............................................................................................................................. 5

1.3 PIN CONNECTION DIAGRAM ............................................................................................................................... 6

2.0 PIN DESCRIPTION ........................................................................................................................................... 7

2.1 RMII INTERFACE FOR REPEATER PORTS............................................................................................................... 7

2.1.1 Repeater Port 0.......................................................................................................................................... 7

2.1.2 Repeater Port 1.......................................................................................................................................... 7

2.1.3 Repeater Port 2.......................................................................................................................................... 8

2.1.4 Repeater Port 3.......................................................................................................................................... 8

2.1.5 Repeater Port 4.......................................................................................................................................... 8

2.1.6 Repeater Port 5.......................................................................................................................................... 8

2.1.7 Repeater Port 6.......................................................................................................................................... 9

2.1.8 Repeater Port 7.......................................................................................................................................... 9

2.2 MII/RMII INTERFACE FOR SWITCH PORTS ........................................................................................................... 9

2.2.1 Switch Port 0.............................................................................................................................................. 9

2.2.2 Switch Port 1............................................................................................................................................ 10

2.3 EXPANSION BUS INTERFACE FOR 100 MBPS....................................................................................................... 11

2.4 EXPANSION BUS INTERFACE FOR 10 MBPS......................................................................................................... 11

2.5 LED DISPLAY.................................................................................................................................................. 12

2.6 BUFFER MEMORY PINS GROUP ........................................................................................................................... 13

2.7 MISCELLANEOUS.............................................................................................................................................. 14

2.8 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 15

3.0 FUNCTIONAL DESCRIPTION ...................................................................................................................... 18

3.1 REPEATER STATE MACHINE.............................................................................................................................. 18

3.2 RXE /TXE CONTROL ...................................................................................................................................... 18

3.3 JABBER STATE MACHINE.................................................................................................................................. 18

3.4 PARTITION STATE MACHINE............................................................................................................................. 18

3.5 OPERATION OF THE BUILT-IN SWITCH............................................................................................................... 19

3.5.1 Packet Filtering and Forwarding Process ................................................................................................ 19

3.5.2 MAC Address Learning and Aging Process .............................................................................................. 19

3.5.3 Flow Control Process............................................................................................................................... 19

3.6 LED DISPLAY INTERFACE ................................................................................................................................ 20

4.0 INTERNAL REGISTERS ................................................................................................................................ 22

5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 23

5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 23

5.2 GENERAL OPERATION CONDITIONS................................................................................................................... 23

5.3 DC CHARACTERISTICS ..................................................................................................................................... 23

5.4 AC SPECIFICATIONS ......................................................................................................................................... 24

5.4.1 LCLK ....................................................................................................................................................... 24

5.4.2 Reset Timing ............................................................................................................................................ 24

5.4.3 RMII Interface Timing TX & RX............................................................................................................... 25

5.4.4 MII Interface Timing TX & RX ................................................................................................................. 26

5.4.5 SRAM read cycle...................................................................................................................................... 27

5.4.6 SRAM write cycle..................................................................................................................................... 28

5.4.7 LED DISPLAY ......................................................................................................................................... 29

5.4.8 LED Display after Reset........................................................................................................................... 29

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