ASIX ELECTRONICS CORPORATION

20

CONFIDENTIAL

AX88872P Swipeater Controller

PRELIMINARY

threshold, the MAC of port will send out a PAUSE frame with maximum delay. The switch will send out a PAUSE

frame with zero delay after below FlowControlActive threshold.

For the receiving channel, the switch will not transmit the next packet whenever received a PAUSE frame with non-zero

delay. The switch will resume packet transmission either after the pause timer expired or a PAUSE frames with zero

delay received.

In half-duplex mode, the switch will receive and transmit the packet in accordance to 802.3 CSMA/CD. If the occupancy

of the buffer memory is above the FlowControlActive threshold, the MAC of port will send out JAM pattern .

3.6 LED Display Interface

AX88872 provides per-port LED status indication for partition, jabber, activity and support rate - based LED

for 10 and 100Mbps segments utilization (%) and switch buffer utilization (%) . All LED[1:0] perform active

low.

LED[1:0] Status Driver Wave-form as follows :

JAB7

JAB6

JAB5

JAB4

JAB3

JAB2

JAB1

JAB0

LED_CK

LED[0]

LED[0]

Continue

LED[1]

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D11

D12

D13

D14

D10

D15

ACT0

ACT1

ACT2

ACT3

ACT4

ACT5

ACT6

ACT7

10M

UTI0

10M

UTI1

10M

UTI2

10M

UTI3

10M

UTI4

10M

UTI5

100M

UTI0

100M

UTI2

100M

UTI3

100M

UTI4

100M

UTI5

100M

UTI1

LED[1]

Continue

PART

7

PART

6

PART

0

PART

1

PART

2

PART

3

PART

4

PART

5

SW

UTI0

SW

UTI1

SW

UTI2

SW

UTI3

SW

UTI4

SW

UTI5

SW

ACT0

SW

ACT1

RID0

RID1

RID2

RID3

D16

D19

D20

D21

D22

D18

D23

D17

( This portation no clock presented )

Chip 0 Memory Test Fail and/or 100M Collision

Chip 1 Memory Test Fail and/or 10M Collision