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AX88872P 数据表(PDF) 9 Page - ASIX Electronics Corporation

部件名 AX88872P
功能描述  10/100BASE Dual Speed ?쏶wipeater??Controller
PDF  36 Pages
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制造商  ASIX [ASIX Electronics Corporation]
网页  http://www.asix.com.tw
标志 ASIX - ASIX Electronics Corporation

AX88872P 数据表(HTML) 9 Page - ASIX Electronics Corporation

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ASIX ELECTRONICS CORPORATION
9
CONFIDENTIAL
AX88872P Swipeater Controller
PRELIMINARY
2.1.7 Repeater Port 6
Signal Name
Type
Pin No.
Description
SPEED6
I
41
Speed Select : Please references section 2.1.1 PORT0 description.
CRS_DV6
I
42
Carrier Sense/Receive Data Valid : Please references section 2.1.1
PORT0 description.
RXD6[1:0]
I
44,43
Receive Data : Please references section 2.1.1 PORT0 description.
TXEN6
O
45
Transmit Enable : Please references section 2.1.1 PORT0 description.
TXD6[1:0]
O
47,46
Transmit Data : Please references section 2.1.1 PORT0 description.
2.1.8 Repeater Port 7
Signal Name
Type
Pin No.
Description
SPEED7
I
49
Speed Select : Please references section 2.1.1 PORT0 description.
CRS_DV7
I
50
Carrier Sense/Receive Data Valid : Please references section 2.1.1
PORT0 description.
RXD7[1:0]
I
52,51
Receive Data : Please references section 2.1.1 PORT0 description.
TXEN7
O
53
Transmit Enable : Please references section 2.1.1 PORT0 description.
TXD7[1:0]
O
55,54
Transmit Data : Please references section 2.1.1 PORT0 description.
2.2 MII/RMII interface for switch ports
2.2.1 Switch Port 0
Signal Name
Type
Pin No.
Description
STXEN0
O
87
Transmit Enable : STXEN0 is transition synchronously with respect
to the rising edge of STXCLK0. STXEN0 indicates that the port is
presenting nibbles on STXD0[3:0] for transmission.
When RMII mode, TXEN is transition synchronously with respect to
the rising edge of REF_CLK. STXEN0 indicates that the port is
presenting nibbles on STXD0[1:0] for transmission.
STXD0[3:0]
O
91,90,89,88
Transmit Data : STXD0[3:0] is transition synchronously with respect
to the rising edge of STXCLK0. For each STXCLK period in which
STXEN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
When RMII mode, STXD0[1:0] shall transition synchronously to
REF_CLK. TXD0[1:0] shall be “00” to indicate idle when TX_EN is
disserted. Value other than “00” are reserved for out-of-band signaling
shall be ignored by PHY. When TX_EN is asserted, TXD[1:0] are
accepted for transmission by PHY
STXCLK0
I
93
Transmit Clock : STXCLK0 is a continuous clock that provides the
timing reference for the transfer of the STXEN0 and STXD0[3:0]
signals from the MII port the switch to the PHY.
SDUPLEX0
I
94
Duplex Select : DUPLEX0 is not standard MII/RMII signal. This
signal is source from PHY to inform switch whether 10M or 100M
speed is auto-negotiated.
SCOL_SP0
I
97
Collision : SCOL_SP0 is input from PHY, when collision is detected.



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