AX88872P datasheet(7/36 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

CONFIDENTIAL

AX88872P Swipeater Controller

PRELIMINARY

2.0 Pin Description

The following terms describe the AX88872 pin out:

All pin names with the “/” suffix are asserted low.

Input

Output

I/O

Input /Output

2.1 RMII interface for repeater ports

2.1.1 Repeater Port 0

Signal Name

Type

Pin No.

Description

SPEED0

160

Speed Select : SPEED0 is not standard RMII signal. This signal is

source from PHY to inform repeater whether 10M or 100M speed is

auto-negotiated. Active for 10Mbps speed is selected depending on

power on configuration.

CRS_DV0

161

Carrier

Sense/Receive

Data

Valid

CRS_DV

asserted

asynchronously on detection of carrier. CRS_DV is asserted by the PHY

when receive medium is non-idle. Loss of carrier shall result in the

desertion of CRS_DV synchronous to the cycle of REF_CLK that

presents the first DI-bits of a nibble on to RXD0[1:0].

RXD0[1:0]

163, 162

Receive Data : RXD0[1:0] is synchronous to REF_CLK

RXD0[1:0] shall be “00” to indicate idle when CRS_DV is disserted.

Value other than “00” are reserved for out-of-band signaling shall be

ignored by MAC Upon assertion of CRS_DV, PHY shall ensure that

RXD[1:0] = “00” until proper receive decoding takes place

TXEN0

165

Transmit Enable : TXEN0 is synchronous to REF_CLK.

TXEN0 indicates that MAC is presenting DI-bits on TXD[1:0] for

transmission. TXEN0 shall be negated prior to the 1st REF_CLK rising

edge following the final DI-bit of a frame

TXD0[1:0]

168, 167

Transmit Data : TXD0[1:0] shall transition synchronously to

REF_CLK. TXD0[1:0] shall be “00” to indicate idle when TX_EN is

disserted. Value other than “00” are reserved for out-of-band signaling

shall be ignored by PHY. When TX_EN is asserted, TXD[1:0] are

accepted for transmission by PHY

2.1.2 Repeater Port 1

Signal Name

Type

Pin No.

Description

SPEED1

169

Speed Select : Please references section 2.1.1 PORT0 description.

CRS_DV1

181

Carrier Sense/Receive Data Valid : Please references section 2.1.1

PORT0 description.

RXD1[1:0]

183, 182

Receive Data : Please references section 2.1.1 PORT0 description.

TXEN1

184

Transmit Enable : Please references section 2.1.1 PORT0 description.

TXD1[1:0]

187, 186

Transmit Data : Please references section 2.1.1 PORT0 description.

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